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SN74LS73D PDF预览

SN74LS73D

更新时间: 2024-11-24 23:03:15
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 触发器
页数 文件大小 规格书
3页 78K
描述
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

SN74LS73D 数据手册

 浏览型号SN74LS73D的Datasheet PDF文件第2页浏览型号SN74LS73D的Datasheet PDF文件第3页 
SN54/74LS73A  
DUAL JK NEGATIVE  
EDGE-TRIGGERED FLIP-FLOP  
The SN54LS/74LS73A offers individual J, K, clear, and clock inputs. These  
dual flip-flops are designed so that when the clock goes HIGH, the inputs are  
enabled and data will be accepted. The logic level of the J and K inputs may  
be allowed to change when the clock pulse is HIGH and the bistable will per-  
form according to the truth table as long as minimum set-up times are ob-  
served. Input data is transferred to the outputs on the negative-going edge of  
the clock pulse.  
DUAL JK NEGATIVE  
EDGE-TRIGGERED FLIP-FLOP  
LOW POWER SCHOTTKY  
LOGIC DIAGRAM (Each Flip-Flop)  
J SUFFIX  
CERAMIC  
CASE 632-08  
14  
1
Q
Q
13 (8)  
12 (9)  
N SUFFIX  
PLASTIC  
CASE 646-06  
CLEAR  
2 (6)  
14  
K
3 (10)  
J
1
14 (7)  
1 (15)  
CLOCK (CP)  
D SUFFIX  
SOIC  
CASE 751A-02  
14  
1
ORDERING INFORMATION  
SN54LSXXJ  
SN74LSXXN  
SN74LSXXD  
Ceramic  
Plastic  
SOIC  
MODE SELECT — TRUTH TABLE  
INPUTS  
OUTPUTS  
OPERATING MODE  
C
J
K
Q
Q
D
LOGIC SYMBOL  
Reset (Clear)  
Toggle  
Load “0” (Reset)  
Load “1” (Set)  
Hold  
L
X
h
l
h
l
X
h
h
l
L
q
L
H
q
H
q
H
L
H
H
H
H
12  
13  
9
14  
1
J
Q
Q
7
5
J
Q
Q
l
q
CP  
K
CP  
K
H, h = HIGH Voltage Level  
L, I = LOW Voltage Level  
X = Don’t Care  
8
3
10  
C
C
D
D
l, h (q) = Lower case letters indicate the state of the referenced input (or output) one set-up time  
l, h (q) = prior to the HIGH to LOW clock transition.  
2
6
V
= PIN 4  
CC  
GND = PIN 11  
FAST AND LS TTL DATA  
5-68  

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