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SN74LS192DR2 PDF预览

SN74LS192DR2

更新时间: 2024-11-23 19:47:27
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 光电二极管
页数 文件大小 规格书
7页 184K
描述
Decade Counter, LS Series, Synchronous, Positive Edge Triggered, 4-Bit, Bidirectional, TTL, PDSO16, SOIC-16

SN74LS192DR2 技术参数

生命周期:Contact Manufacturer包装说明:SOP,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.61计数方向:BIDIRECTIONAL
系列:LSJESD-30 代码:R-PDSO-G16
长度:9.9 mm负载/预设输入:YES
逻辑集成电路类型:DECADE COUNTER工作模式:SYNCHRONOUS
位数:4功能数量:1
端子数量:16最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE传播延迟(tpd):47 ns
座面最大高度:1.75 mm最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
触发器类型:POSITIVE EDGE宽度:3.9 mm
最小 fmax:25 MHzBase Number Matches:1

SN74LS192DR2 数据手册

 浏览型号SN74LS192DR2的Datasheet PDF文件第2页浏览型号SN74LS192DR2的Datasheet PDF文件第3页浏览型号SN74LS192DR2的Datasheet PDF文件第4页浏览型号SN74LS192DR2的Datasheet PDF文件第5页浏览型号SN74LS192DR2的Datasheet PDF文件第6页浏览型号SN74LS192DR2的Datasheet PDF文件第7页 
SN74LS192  
PRESETTABLE BCDꢀ/ꢀDECADE  
UPꢀ/ꢀDOWN COUNTER  
PRESETTABLE 4-BIT  
BINARY UPꢀ/ꢀDOWN  
COUNTER  
http://onsemi.com  
The SN54/74LS192 is an UP/DOWN BCD Decade (8421) Counter  
and the SN54/74LS193 is an UP/DOWN MODULO-16 Binary  
Counter. Separate Count Up and Count Down Clocks are used and in  
either counting mode the circuits operate synchronously. The outputs  
change state synchronous with the LOW-to-HIGH transitions on the  
clock inputs.  
PRESETTABLE BCD/DECADE  
UP/DOWN COUNTER  
PRESETTABLE 4-BIT BINARY  
UP/DOWN COUNTER  
Separate Terminal Count Up and Terminal Count Down outputs are  
provided which are used as the clocks for a subsequent stages without  
extra logic, thus simplifying multistage counter designs. Individual  
preset inputs allow the circuits to be used as programmable counters.  
Both the Parallel Load (PL) and the Master Reset (MR) inputs  
asynchronously override the clocks.  
LOW POWER SCHOTTKY  
J SUFFIX  
CERAMIC  
CASE 620-09  
Low Power . . . 95 mW Typical Dissipation  
High Speed . . . 40 MHz Typical Count Frequency  
Synchronous Counting  
16  
1
Asynchronous Master Reset and Parallel Load  
Individual Preset Inputs  
Cascading Circuitry Internally Provided  
N SUFFIX  
PLASTIC  
CASE 648-08  
16  
1
CONNECTION DIAGRAM DIP (TOP VIEW)  
V
P
MR TC  
TC  
PL  
P
P
3
D SUFFIX  
CC  
0
D
U
2
SOIC  
CASE 751B-03  
16  
15  
14  
13  
12  
11  
10  
9
16  
1
NOTE:  
The Flatpak version  
has the same pinouts  
(Connection Diagram) as the Dual  
In-Line Package.  
ORDERING INFORMATION  
SN54LSXXXJ  
Ceramic  
SN74LSXXXN Plastic  
SN74LSXXXD SOIC  
1
2
3
4
5
6
8
7
P
Q
Q
CP  
CP  
Q
Q
3
GND  
1
1
0
D
U
2
LOGIC SYMBOL  
PIN NAMES  
LOADING (Note a)  
11 15  
1
10  
9
HIGH  
LOW  
CP  
CP  
MR  
PL  
Count Up Clock Pulse Input  
Count Down Clock Pulse Input  
Asynchronous Master Reset (Clear) Input  
Asynchronous Parallel Load (Active LOW) Input 0.5 U.L.  
Parallel Data Inputs  
Flip-Flop Outputs (Note b)  
Terminal Count Down (Borrow) Output (Note b)  
Terminal Count Up (Carry) Output (Note b)  
0.5 U.L.  
0.5 U.L.  
0.5 U.L.  
0.25 U.L.  
0.25 U.L.  
0.25 U.L.  
0.25 U.L.  
0.25 U.L.  
U
D
PL  
P
P
P
P
0
1
2
3
12  
13  
CP  
U
TC  
5
4
U
P
0.5 U.L.  
n
CP  
TC  
D
D
Q
10 U.L. 5 (2.5) U.L.  
10 U.L. 5 (2.5) U.L.  
10 U.L. 5 (2.5) U.L.  
n
MR Q  
Q
Q
6
Q
2 3  
0
1
TC  
TC  
D
U
NOTES:  
a. 1 TTL Unit Load (U.L.) = 40 μA HIGH/1.6 mA LOW.  
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)  
b. Temperature Ranges.  
14  
3
2
7
V
= PIN 16  
CC  
GND = PIN 8  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
July, 2006 Rev. 7  
SN74LS192/D  

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