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SN74LS192N PDF预览

SN74LS192N

更新时间: 2024-01-15 07:12:06
品牌 Logo 应用领域
安森美 - ONSEMI 计数器触发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
7页 114K
描述
PRESETTABLE BCD/DECADE UP/DOWN COUNTER PRESETTABLE 4-BIT BINARY UP/DOWN COUNTER

SN74LS192N 数据手册

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SN54/74LS192  
SN54/74LS193  
PRESETTABLE BCD/DECADE  
UP/DOWN COUNTER  
PRESETTABLE 4-BIT BINARY  
UP/DOWN COUNTER  
PRESETTABLE BCD/DECADE  
UP/DOWN COUNTER  
PRESETTABLE 4-BIT BINARY  
UP/DOWN COUNTER  
The SN54/74LS192 is an UP/DOWN BCD Decade (8421) Counter and the  
SN54/74LS193 is an UP/DOWN MODULO-16 Binary Counter. Separate  
Count Up and Count Down Clocks are used and in either counting mode the  
circuits operate synchronously. The outputs change state synchronous with  
the LOW-to-HIGH transitions on the clock inputs.  
LOW POWER SCHOTTKY  
Separate Terminal Count Up and Terminal Count Down outputs are  
provided which are used as the clocks for a subsequent stages without extra  
logic, thus simplifying multistage counter designs. Individual preset inputs  
allow the circuits to be used as programmable counters. Both the Parallel  
Load (PL) and the Master Reset (MR) inputs asynchronously override the  
clocks.  
J SUFFIX  
CERAMIC  
CASE 620-09  
16  
1
Low Power . . . 95 mW Typical Dissipation  
High Speed . . . 40 MHz Typical Count Frequency  
Synchronous Counting  
Asynchronous Master Reset and Parallel Load  
Individual Preset Inputs  
N SUFFIX  
PLASTIC  
CASE 648-08  
16  
1
Cascading Circuitry Internally Provided  
Input Clamp Diodes Limit High Speed Termination Effects  
D SUFFIX  
SOIC  
CASE 751B-03  
CONNECTION DIAGRAM DIP (TOP VIEW)  
16  
1
V
P
MR  
14  
TC  
TC  
PL  
11  
P
P
3
CC  
16  
0
D
U
2
15  
13  
12  
10  
9
ORDERING INFORMATION  
NOTE:  
SN54LSXXXJ  
SN74LSXXXN Plastic  
SN74LSXXXD SOIC  
Ceramic  
The Flatpak version  
has the same pinouts  
(Connection Diagram) as  
the Dual In-Line Package.  
1
2
3
4
5
6
8
7
P
1
Q
1
Q
0
CP  
CP  
Q
Q
GND  
LOGIC SYMBOL  
D
U
2
3
11 15  
1
10  
9
PIN NAMES  
LOADING (Note a)  
HIGH  
LOW  
PL  
P
P
P
P
3
0
1
2
12  
13  
CP  
TC  
CP  
CP  
MR  
PL  
Count Up Clock Pulse Input  
Count Down Clock Pulse Input  
Asynchronous Master Reset (Clear) Input  
Asynchronous Parallel Load (Active LOW) Input  
Parallel Data Inputs  
Flip-Flop Outputs (Note b)  
Terminal Count Down (Borrow) Output (Note b)  
Terminal Count Up (Carry) Output (Note b)  
0.5 U.L.  
0.5 U.L.  
0.5 U.L.  
0.5 U.L.  
0.5 U.L.  
0.25 U.L.  
0.25 U.L.  
0.25 U.L.  
0.25 U.L.  
0.25 U.L.  
5
4
U
U
U
D
CP  
TC  
D
D
MR Q  
Q
Q
Q
2 3  
0
1
P
Q
TC  
TC  
n
n
10 U.L. 5 (2.5) U.L.  
10 U.L. 5 (2.5) U.L.  
10 U.L. 5 (2.5) U.L.  
D
U
14  
3
2
6
7
V
= PIN 16  
CC  
GND = PIN 8  
NOTES:  
a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.  
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)  
b. Temperature Ranges.  
FAST AND LS TTL DATA  
5-1  

SN74LS192N 替代型号

型号 品牌 替代类型 描述 数据表
HD74LS190P RENESAS

功能相似

Synchronous Up / Down Decade Counter (signal clock line)

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