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SN74HCT125DTE4 PDF预览

SN74HCT125DTE4

更新时间: 2024-11-26 10:20:23
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
12页 592K
描述
HCT SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDSO14, GREEN, PLASTIC, SOIC-14

SN74HCT125DTE4 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP14,.25针数:14
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.26控制类型:ENABLE LOW
系列:HCTJESD-30 代码:R-PDSO-G14
JESD-609代码:e4长度:8.65 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.006 A湿度敏感等级:1
位数:1功能数量:4
端口数量:2端子数量:14
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP14,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:5 V
Prop。Delay @ Nom-Sup:33 ns传播延迟(tpd):46 ns
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3.9 mm

SN74HCT125DTE4 数据手册

 浏览型号SN74HCT125DTE4的Datasheet PDF文件第2页浏览型号SN74HCT125DTE4的Datasheet PDF文件第3页浏览型号SN74HCT125DTE4的Datasheet PDF文件第4页浏览型号SN74HCT125DTE4的Datasheet PDF文件第5页浏览型号SN74HCT125DTE4的Datasheet PDF文件第6页浏览型号SN74HCT125DTE4的Datasheet PDF文件第7页 
SN54HCT125, SN74HCT125  
QUADRUPLE BUS BUFFER GATES  
WITH 3-STATE OUTPUTS  
SCLS069E – NOVEMBER 1988 – REVISED AUGUST 2003  
Operating Voltage Range of 4.5 V to 5.5 V  
6-mA Output Drive at 5 V  
High-Current Outputs Drive Up To 15  
LSTTL Loads  
Low Input Current of 1 µA Max  
Inputs Are TTL-Voltage Compatible  
Low Power Consumption, 80-µA Max I  
CC  
High-Current 3-State Outputs Drive Bus  
Lines or Buffer Memory Address Registers  
Typical t = 12 ns  
pd  
SN54HCT125 . . . FK PACKAGE  
(TOP VIEW)  
SN54HCT125 . . . J OR W PACKAGE  
SN74HCT125 . . . D OR N PACKAGE  
(TOP VIEW)  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
1OE  
1A  
1Y  
2OE  
2A  
2Y  
V
CC  
4OE  
4A  
3
2
1
20 19  
18  
4A  
NC  
4Y  
1Y  
NC  
4
5
6
7
8
17  
16  
4Y  
3OE  
3A  
2OE  
NC  
15 NC  
14  
9 10 11 12 13  
3OE  
2A  
8
GND  
3Y  
NC – No internal connection  
description/ordering information  
These bus buffer gates feature independent line drivers with 3-state outputs. Each output is disabled when the  
associated output-enable (OE) input is high.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP – N  
SOIC – D  
Tube of 25  
Tube of 50  
Reel of 2500  
Reel of 250  
Tube of 25  
Tube of 150  
Tube of 55  
SN74HCT125N  
SN74HCT125D  
SN74HCT125DR  
SN74HCT125DT  
SNJ54HCT125J  
SNJ54HCT125W  
SNJ54HCT125FK  
SN74HCT125N  
–40°C to 85°C  
HCT125  
CDIP – J  
CFP – W  
LCCC – FK  
SNJ54HCT125J  
SNJ54HCT125W  
SNJ54HCT125FK  
–55°C to 125°C  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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