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SN74HCT126N PDF预览

SN74HCT126N

更新时间: 2024-10-02 12:57:51
品牌 Logo 应用领域
德州仪器 - TI 输出元件
页数 文件大小 规格书
5页 95K
描述
Quadruple Bus Buffer Gates With 3-State Outputs 14-PDIP -40 to 85

SN74HCT126N 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:DIP
包装说明:DIP, DIP14,.3针数:14
Reach Compliance Code:not_compliant风险等级:5.45
控制类型:ENABLE HIGH系列:HCT
JESD-30 代码:R-PDIP-T14长度:19.305 mm
逻辑集成电路类型:BUS DRIVER位数:1
功能数量:4端口数量:2
端子数量:14最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP14,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
传播延迟(tpd):46 ns认证状态:Not Qualified
座面最大高度:5.08 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:INDUSTRIAL
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

SN74HCT126N 数据手册

 浏览型号SN74HCT126N的Datasheet PDF文件第2页浏览型号SN74HCT126N的Datasheet PDF文件第3页浏览型号SN74HCT126N的Datasheet PDF文件第4页浏览型号SN74HCT126N的Datasheet PDF文件第5页 
SN54HCT126, SN74HCT126  
QUADRUPLE BUS BUFFER GATES  
WITH 3-STATE OUTPUTS  
SCLS070A – NOVEMBER 1988 – REVISED NOVEMBER 1990  
SN54HCT126 . . . J PACKAGE  
SN74HCT126 . . . D OR N PACKAGE  
(TOP VIEW)  
High-Current 3-State Outputs Drive Bus  
Lines or Buffer Memory Address Registers  
Inputs Are TTL-Voltage Compatible  
Package Options Include Plastic  
Small-Outline (D) Packages, Ceramic Chip  
Carriers (FK), and Standard Plastic (N) and  
Ceramic (J) 300-mil DIPs  
1OE  
1A  
V
CC  
4OE  
4A  
1
2
3
4
5
6
7
14  
13  
12  
11  
1Y  
2OE  
2A  
4Y  
10 3OE  
description  
9
8
2Y  
3A  
3Y  
GND  
These bus buffers feature independent line  
drivers with 3-state outputs. Each output is  
disabled when the associated OE is low.  
SN54HCT126 . . . FK PACKAGE  
(TOP VIEW)  
The SN54HCT126 is characterized for operation  
over the full military temperature range of –55°C  
to 125°C. The SN74HCT126 is characterized for  
operation from –40°C to 85°C.  
3
2
1
20 19  
18  
4A  
NC  
4Y  
1Y  
NC  
4
5
6
7
8
17  
16  
FUNCTION TABLE  
2OE  
NC  
INPUTS  
OUTPUT  
Y
15 NC  
14  
9 10 11 12 13  
OE  
A
H
L
3OE  
2A  
H
H
L
H
L
X
Z
H = high level, L = low level,  
X = irrelevant  
NC – No internal connection  
logic symbol  
logic diagram, each buffer (positive logic)  
1
OE  
1OE  
3
6
EN  
1Y  
2Y  
3Y  
4Y  
2
1A  
4
A
Y
2OE  
5
2A  
10  
8
3OE  
9
3A  
13  
4OE  
11  
12  
4A  
This symbol is in accordance with ANSI/IEEE Std 91-1984 and  
IEC Publication 617-12.  
Pin numbers shown are for the D, J, and N packages.  
Copyright 1990, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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