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SN74HC573APWTG4 PDF预览

SN74HC573APWTG4

更新时间: 2024-11-02 05:04:47
品牌 Logo 应用领域
德州仪器 - TI 锁存器输出元件
页数 文件大小 规格书
18页 633K
描述
OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

SN74HC573APWTG4 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP, TSSOP20,.25针数:20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.3其他特性:BROADSIDE VERSION OF 373
系列:HC/UHJESD-30 代码:R-PDSO-G20
JESD-609代码:e4长度:6.5 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.006 A湿度敏感等级:1
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP20,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TR
峰值回流温度(摄氏度):260电源:2/6 V
Prop。Delay @ Nom-Sup:20 ns传播延迟(tpd):285 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:FF/Latches最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4.4 mmBase Number Matches:1

SN74HC573APWTG4 数据手册

 浏览型号SN74HC573APWTG4的Datasheet PDF文件第2页浏览型号SN74HC573APWTG4的Datasheet PDF文件第3页浏览型号SN74HC573APWTG4的Datasheet PDF文件第4页浏览型号SN74HC573APWTG4的Datasheet PDF文件第5页浏览型号SN74HC573APWTG4的Datasheet PDF文件第6页浏览型号SN74HC573APWTG4的Datasheet PDF文件第7页 
ꢀꢁ ꢂꢃ ꢄꢅ ꢂ ꢆꢇ ꢈ ꢉ ꢀꢁꢆ ꢃꢄ ꢅꢂ ꢆꢇ ꢈ  
ꢊ ꢅꢋꢈꢌ ꢋ ꢍꢈꢁꢀ ꢎꢈꢍꢏ ꢁꢋ ꢐꢑꢋ ꢒꢎ ꢏ ꢌꢈꢋꢅ ꢄ ꢏꢀ  
ꢓ ꢔꢋ ꢄ ꢇ ꢑꢀꢋꢈꢋ ꢏ ꢊ ꢕꢋ ꢎꢕ ꢋꢀ  
SCLS147E − DECEMBER 1982 − REVISED SEPTEMBER 2003  
D
D
D
Wide Operating Voltage Range of 2 V to 6 V  
D
Typical t = 21 ns  
pd  
High-Current 3-State Outputs Drive Bus  
Lines Directly or Up To 15 LSTTL Loads  
D
D
D
6-mA Output Drive at 5 V  
Low Input Current of 1 µA Max  
Bus-Structured Pinout  
Low Power Consumption, 80-µA Max I  
CC  
SN54HC573A . . . J OR W PACKAGE  
SN74HC573A . . . DB, DW, N, OR PW PACKAGE  
(TOP VIEW)  
SN54HC573A . . . FK PACKAGE  
(TOP VIEW)  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
V
CC  
1Q  
2Q  
1
2
3
4
5
6
7
8
9
20  
19  
18  
3
2
1
20 19  
18  
2Q  
3Q  
4Q  
5Q  
6Q  
3D  
4D  
5D  
6D  
7D  
4
5
6
7
8
17  
16  
15  
14  
17 3Q  
16 4Q  
15 5Q  
14 6Q  
13 7Q  
12 8Q  
11 LE  
9 10 11 12 13  
GND 10  
description/ordering information  
These octal transparent D-type latches feature 3-state outputs designed specifically for driving highly capacitive  
or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports,  
bidirectional bus drivers, and working registers.  
While the latch-enable (LE) input is high, the Q outputs respond to the data (D) inputs. When LE is low, the  
outputs are latched to retain the data that was set up.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high  
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive  
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines  
without interface or pullup components.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP − N  
Tube of 25  
Tube of 40  
Reel of 2500  
Reel of 2000  
Reel of 2000  
Reel of 250  
Tube of 25  
Tube of 150  
Tube of 55  
SN74HC573AN  
SN74HC573AN  
SN74HC573ADW  
SN74HC573ADWR  
SN74HC573ADBR  
SN74HC573APWR  
SN74HC573APWT  
SNJ54HC573AJ  
SOIC − DW  
SSOP − DB  
HC573A  
HC573A  
−40°C to 85°C  
TSSOP − PW  
HC573A  
CDIP − J  
CFP − W  
LCCC − FK  
SNJ54HC573AJ  
SNJ54HC573AW  
SNJ54HC573AFK  
−55°C to 125°C  
SNJ54HC573AW  
SNJ54HC573AFK  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
ꢊ ꢗ ꢢ ꢚ ꢙꢥ ꢠꢟ ꢝꢞ ꢟꢙ ꢛꢢ ꢤꢖ ꢜꢗ ꢝ ꢝꢙ ꢬꢔ ꢌꢑ ꢎꢍ ꢭ ꢑꢇꢮꢂ ꢇꢂꢉ ꢜꢤꢤ ꢢꢜ ꢚ ꢜ ꢛꢡ ꢝꢡꢚ ꢞ ꢜ ꢚ ꢡ ꢝꢡ ꢞꢝꢡ ꢥ  
ꢝ ꢡ ꢞ ꢝꢖ ꢗꢫ ꢙꢘ ꢜ ꢤꢤ ꢢꢜ ꢚ ꢜ ꢛ ꢡ ꢝ ꢡ ꢚ ꢞ ꢦ  
ꢠ ꢗꢤ ꢡꢞꢞ ꢙ ꢝꢧꢡ ꢚ ꢩꢖ ꢞꢡ ꢗ ꢙꢝꢡ ꢥꢦ ꢊ ꢗ ꢜꢤ ꢤ ꢙ ꢝꢧꢡ ꢚ ꢢꢚ ꢙ ꢥꢠꢟ ꢝꢞ ꢉ ꢢꢚ ꢙ ꢥꢠꢟ ꢝꢖꢙ ꢗ  
ꢙꢟ  
ꢙꢡ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74HC573APWTG4 替代型号

型号 品牌 替代类型 描述 数据表
MM74HC573MTC ONSEMI

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OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

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SN74HC573N-00 TI

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SN74HC573NP1 TI

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IC,LATCH,SINGLE,8-BIT,HC-CMOS,DIP,20PIN,PLASTIC