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SN74HC112D PDF预览

SN74HC112D

更新时间: 2024-10-31 23:03:11
品牌 Logo 应用领域
德州仪器 - TI 触发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
7页 97K
描述
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

SN74HC112D 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP, SOP16,.25针数:16
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:0.99
系列:HC/UHJESD-30 代码:R-PDSO-G16
JESD-609代码:e4长度:9.9 mm
负载电容(CL):50 pF逻辑集成电路类型:J-K FLIP-FLOP
最大频率@ Nom-Sup:20000000 Hz最大I(ol):0.004 A
湿度敏感等级:1位数:2
功能数量:2端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TUBE峰值回流温度(摄氏度):260
电源:2/6 V最大电源电流(ICC):0.04 mA
Prop。Delay @ Nom-Sup:41 ns传播延迟(tpd):155 ns
认证状态:Not Qualified施密特触发器:No
座面最大高度:1.75 mm子类别:FF/Latches
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:NEGATIVE EDGE
宽度:3.91 mm最小 fmax:24 MHz
Base Number Matches:1

SN74HC112D 数据手册

 浏览型号SN74HC112D的Datasheet PDF文件第2页浏览型号SN74HC112D的Datasheet PDF文件第3页浏览型号SN74HC112D的Datasheet PDF文件第4页浏览型号SN74HC112D的Datasheet PDF文件第5页浏览型号SN74HC112D的Datasheet PDF文件第6页浏览型号SN74HC112D的Datasheet PDF文件第7页 
SN54HC112, SN74HC112  
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS  
WITH CLEAR AND PRESET  
SCLS099C – DECEMBER 1982 – REVISED APRIL 1999  
SN54HC112 . . . J OR W PACKAGE  
SN74HC112 . . . D OR N PACKAGE  
(TOP VIEW)  
Package Options Include Plastic  
Small-Outline (D) and Ceramic Flat (W)  
Packages, Ceramic Chip Carriers (FK), and  
Standard Plastic (N) and Ceramic (J) DIPs  
1CLK  
1K  
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
1CLR  
2CLR  
2CLK  
description  
1J  
1PRE  
1Q  
The ’HC112 devices contain two independent J-K  
negative-edge-triggered flip-flops. A low level at  
the preset (PRE) or clear (CLR) inputs sets or  
resets the outputs regardless of the levels of the  
other inputs. When PRE and CLR are inactive  
(high), data at the J and K inputs meeting the  
setup time requirements are transferred to the  
outputs on the negative-going edge of the clock  
(CLK) pulse. Clock triggering occurs at a voltage  
level and is not directly related to the rise time of  
CLK. Following the hold-time interval, data at the  
J and K inputs may be changed without affecting  
the levels at the outputs. These versatile flip-flops  
perform as toggle flip-flops by tying J and K high.  
12 2K  
11  
10  
9
1Q  
2J  
2Q  
2PRE  
2Q  
GND  
SN54HC112 . . . FK PACKAGE  
(TOP VIEW)  
3
2
1
20 19  
18  
2CLR  
2CLK  
NC  
1J  
1PRE  
NC  
4
5
6
7
8
17  
16  
The SN54HC112 is characterized for operation  
over the full military temperature range of –55°C  
to 125°C. The SN74HC112 is characterized for  
operation from –40°C to 85°C.  
15 2K  
14  
9 10 11 12 13  
1Q  
2J  
1Q  
NC – No internal connection  
FUNCTION TABLE  
INPUTS  
OUTPUTS  
PRE  
L
CLR  
H
CLK  
X
J
X
X
X
L
K
X
X
X
L
Q
H
L
Q
L
H
L
X
H
H
L
L
X
H
H
H
Q
Q
0
0
H
H
H
L
L
H
L
H
H
H
H
X
L
H
H
H
H
X
Toggle  
H
H
H
Q
Q
0
0
This configuration is unstable; that is, it does not persist  
when either PRE or CLR returns to its inactive (high) level.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74HC112D 替代型号

型号 品牌 替代类型 描述 数据表
SN74HC109NSR TI

类似代替

具有清零和预置端的双路负边沿触发式 J-K 触发器 | NS | 16 | -40 to
SN74HC112DT TI

类似代替

DUAL J-NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

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