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SN74CBTLV3251DRG4 PDF预览

SN74CBTLV3251DRG4

更新时间: 2024-11-06 04:48:59
品牌 Logo 应用领域
德州仪器 - TI 解复用器
页数 文件大小 规格书
17页 739K
描述
LOW-VOLTAGE 1-OF-8 FET MULTIPLEXER/DEMULTIPLEXER

SN74CBTLV3251DRG4 数据手册

 浏览型号SN74CBTLV3251DRG4的Datasheet PDF文件第2页浏览型号SN74CBTLV3251DRG4的Datasheet PDF文件第3页浏览型号SN74CBTLV3251DRG4的Datasheet PDF文件第4页浏览型号SN74CBTLV3251DRG4的Datasheet PDF文件第5页浏览型号SN74CBTLV3251DRG4的Datasheet PDF文件第6页浏览型号SN74CBTLV3251DRG4的Datasheet PDF文件第7页 
ꢀꢁꢂ ꢃ ꢄ ꢅꢆ ꢇꢈ ꢉꢊ ꢋꢌ  
ꢇꢍ ꢎꢏꢈꢍ ꢇꢆꢐꢑ ꢒ ꢌ ꢏꢍ ꢓꢏ ꢔ ꢓ ꢒꢆ ꢕ ꢖꢇꢆ ꢗꢘ ꢇꢒ ꢙꢒꢚꢛ ꢜꢒꢕ ꢖꢇꢆꢗ ꢘ ꢇꢒ ꢙꢒ ꢚ  
SCDS054I − MARCH 1998 − REVISED OCTOBER 2003  
D
D
D
5-Switch Connection Between Two Ports  
Rail-to-Rail Switching on Data I/O Ports  
D
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
I
Supports Partial-Power-Down Mode  
off  
Operation  
D, DBQ, DGV, OR PW PACKAGE  
(TOP VIEW)  
RGY PACKAGE  
(TOP VIEW)  
V
B4  
B3  
B2  
B1  
A
NC  
OE  
GND  
1
2
3
4
5
6
7
8
16  
CC  
15 B5  
14 B6  
13 B7  
12 B8  
1
16  
B3  
B2  
B1  
A
NC  
OE  
15  
14  
13  
12  
11  
10  
2
3
4
5
6
7
B5  
B6  
B7  
B8  
S0  
S1  
11  
10  
9
S0  
S1  
S2  
8
9
NC − No internal connection  
NC − No internal connection  
description/ordering information  
The SN74CBTLV3251 device is a 1-of-8 high-speed FET multiplexer/demultiplexer. The low on-state resistance  
of the switch allows connections to be made with minimal propagation delay.  
The select inputs (S0, S1, S2) control the data flow. The FET multiplexers/demultiplexers are disabled when  
the output-enable (OE) input is high.  
This device is fully specified for partial-power-down applications using I . The I feature ensures that  
off  
off  
damaging current will not backflow through the device when it is powered down. The device has isolation during  
power off.  
To ensure the high-impedance state during power up or power down, OE should be tied to V  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
through a pullup  
CC  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
QFN − RGY  
SOIC − D  
Tape and reel  
SN74CBTLV3251RGYR  
SN74CBTLV3251D  
CL251  
Tube  
CBTLV3251  
Tape and reel  
SN74CBTLV3251DR  
SN74CBTLV3251DBQR  
SN74CBTLV3251PWR  
SN74CBTLV3251DGVR  
−40°C to 85°C  
SSOP (QSOP) − DBQ Tape and reel  
CL251  
CL251  
CL251  
TSSOP − PW  
TVSOP − DGV  
Tape and reel  
Tape and reel  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines  
are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢆꢨ  
Copyright 2003, Texas Instruments Incorporated  
ꢤ ꢨ ꢥ ꢤꢝ ꢞꢲ ꢠꢟ ꢣ ꢫꢫ ꢩꢣ ꢡ ꢣ ꢢ ꢨ ꢤ ꢨ ꢡ ꢥ ꢭ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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