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SN74CBT16245CDGVRE4 PDF预览

SN74CBT16245CDGVRE4

更新时间： 2024-12-01 19:45:15
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
11页 183K
描述
IC,BUS SWITCH,CMOS,TSSOP,48PIN,PLASTIC

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SN74CBT16245CDGVRE4 技术参数

生命周期：Obsolete包装说明：TSSOP, TSSOP48,.25,16
Reach Compliance Code：unknown风险等级：5.84
JESD-30 代码：R-PDSO-G48逻辑集成电路类型：BUS DRIVER
端子数量：48最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP48,.25,16
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
电源：5 V认证状态：Not Qualified
子类别：Bus Driver/Transceivers标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.4 mm端子位置：DUAL
Base Number Matches：1

SN74CBT16245CDGVRE4 数据手册

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SCDS139 − OCTOBER 2003  
DGG, DGV, OR DL PACKAGE  
(TOP VIEW)  
D
D
D
D
D
Member of the Texas Instruments  
WidebusFamily  
Undershoot Protection for Off-Isolation on  
A and B Ports Up to −2 V  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
NC  
1B1  
1B2  
GND  
1B3  
1B4  
1OE  
1A1  
1A2  
GND  
1A3  
1A4  
2
Bidirectional Data Flow, With Near-Zero  
Propagation Delay  
3
4
Low ON-State Resistance (r  
)
5
on  
Characteristics (r = 3 Ω Typical)  
6
on  
7
V
V
Low Input/Output Capacitance Minimizes  
Loading and Signal Distortion  
CC  
CC  
8
1B5  
1B6  
GND  
1B7  
1B8  
2B1  
2B2  
GND  
2B3  
2B4  
1A5  
1A6  
GND  
1A7  
1A8  
2A1  
2A2  
GND  
2A3  
2A4  
9
(C  
= 5.5 pF Typical)  
io(OFF)  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
D
D
Data and Control Inputs Provide  
Undershoot Clamp Diodes  
Low Power Consumption  
(I  
= 3 µA Max)  
CC  
D
V
Operating Range From 4 V to 5.5 V  
CC  
D
Data I/Os Support 0 to 5-V Signaling Levels  
(0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)  
V
V
D
D
D
D
Control Inputs Can be Driven by TTL or  
5-V/3.3-V CMOS Outputs  
CC  
CC  
2B5  
2B6  
GND  
2B7  
2B8  
NC  
2A5  
2A6  
GND  
2A7  
2A8  
2OE  
I
Supports Partial-Power-Down Mode  
off  
Operation  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
ESD Performance Tested Per JESD 22  
− 2000-V Human-Body Model  
(A114-B, Class II)  
NC − No internal connection  
− 1000-V Charged-Device Model (C101)  
D
Supports Both Digital and Analog  
Applications: PCI Interface, Memory  
Interleaving, Bus Isolation, Low-Distortion  
Signal Gating  
description/ordering information  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
Tube  
SN74CBT16245CDL  
SSOP − DL  
CBT16245C  
Tape and reel  
Tube  
SN74CBT16245CDLR  
SN74CBT16245CDGG  
SN74CBT16245CDGGR  
SN74CBT16245CDGVR  
−40°C to 85°C  
TSSOP − DGG  
TVSOP − DGV  
CBT16245C  
CY245C  
Tape and reel  
Tape and reel  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments.  
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Copyright 2003, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...11

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