5秒后页面跳转
SN74AS652NTE4 PDF预览

SN74AS652NTE4

更新时间: 2024-11-16 07:54:39
品牌 Logo 应用领域
德州仪器 - TI 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
34页 906K
描述
AS SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDIP24, ROHS COMPLIANT, PLASTIC, DIP-24

SN74AS652NTE4 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:DIP
包装说明:DIP, DIP24,.3针数:24
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.44控制类型:INDEPENDENT CONTROL
计数方向:BIDIRECTIONAL系列:AS
JESD-30 代码:R-PDIP-T24JESD-609代码:e4
长度:31.64 mm逻辑集成电路类型:REGISTERED BUS TRANSCEIVER
最大I(ol):0.048 A位数:8
功能数量:1端口数量:2
端子数量:24最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP24,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
最大电源电流(ICC):211 mAProp。Delay @ Nom-Sup:9 ns
传播延迟(tpd):9 ns认证状态:Not Qualified
座面最大高度:5.08 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:TTL温度等级:COMMERCIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED翻译:N/A
触发器类型:POSITIVE EDGE宽度:7.62 mm

SN74AS652NTE4 数据手册

 浏览型号SN74AS652NTE4的Datasheet PDF文件第2页浏览型号SN74AS652NTE4的Datasheet PDF文件第3页浏览型号SN74AS652NTE4的Datasheet PDF文件第4页浏览型号SN74AS652NTE4的Datasheet PDF文件第5页浏览型号SN74AS652NTE4的Datasheet PDF文件第6页浏览型号SN74AS652NTE4的Datasheet PDF文件第7页 
SN54ALS652, SN54ALS653, SN54AS651, SN54AS652  
SN74ALS651A, SN74ALS652A, SN74ALS653, SN74ALS654, SN74AS651, SN74AS652  
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS  
SDAS066G – DECEMBER 1983 – REVISED DECEMBER 2000  
SN54ALS, SN54AS. . . JT PACKAGE  
SN74ALS, SN74AS. . . DW OR NT PACKAGE  
Bus Transceivers/Registers  
Independent Registers and Enables for A  
(TOP VIEW)  
and B Buses  
CLKAB  
SAB  
OEAB  
A1  
V
CC  
Multiplexed Real-Time and Stored Data  
Choice of True or Inverting Data Paths  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
CLKBA  
SBA  
OEBA  
B1  
2
3
Choice of 3-State or Open-Collector  
Outputs to A Bus  
4
A2  
5
A3  
B2  
6
DEVICE  
A OUTPUT  
B OUTPUT  
LOGIC  
A4  
B3  
7
SN74ALS651A,  
’AS651  
A5  
B4  
3-State  
3-State  
Inverting  
8
A6  
B5  
9
SN54ALS652,  
SN74ALS652A,  
’AS652  
A7  
B6  
10  
11  
3-State  
3-State  
True  
A8  
B7  
GND 12  
13 B8  
’ALS653  
Open Collector  
Open Collector  
3-State  
3-State  
Inverting  
True  
SN74ALS654  
SN54ALS, SN54AS. . . FK PACKAGE  
(TOP VIEW)  
description  
These devices consist of bus-transceiver circuits,  
D-type flip-flops, and control circuitry arranged for  
multiplexed transmission of data directly from the  
data bus or from the internal storage registers.  
Output-enable (OEAB and OEBA) inputs are  
provided to control the transceiver functions.  
Select-control (SAB and SBA) inputs are provided  
to select real-time or stored data transfer. The  
circuitry used for select control eliminates the  
typical decoding glitch that occurs in a multiplexer  
during the transition between stored and real-time  
data. A low input level selects real-time data, and  
a high input level selects stored data. Figure 1  
illustrates the four fundamental bus-management  
functions that can be performed with the octal bus  
transceivers and registers  
4
3
2 1 28 27 26  
5
6
7
8
9
25 OEBA  
A1  
A2  
A3  
NC  
A4  
A5  
A6  
24  
23  
22  
21  
20  
19  
B1  
B2  
NC  
B3  
B4  
B5  
10  
11  
12 13 14 15 16 17 18  
NC – No internal connection  
Data on the A or B data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions at  
the appropriate clock (CLKAB or CLKBA) terminals, regardless of the select- or output-control terminals. When  
SAB and SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type  
flip-flops by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input.  
When all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains  
at its last state.  
The -1 versions of the SN74ALS651A and SN74ALS652A are identical to the standard versions except that the  
recommended maximum I  
SN54ALS652, SN54ALS653, SN74ALS653, and SN74ALS654.  
for the -1 versions is increased to 48 mA. There are no -1 versions of the  
OL  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2000, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74AS652NTE4 替代型号

型号 品牌 替代类型 描述 数据表
SN74AS652NT TI

完全替代

OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SN74AS652DW TI

完全替代

OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SN54AS652JT TI

完全替代

OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

与SN74AS652NTE4相关器件

型号 品牌 获取价格 描述 数据表
SN74AS74A TI

获取价格

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SN74AS74AD TI

获取价格

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SN74AS74ADE4 TI

获取价格

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SN74AS74ADG4 TI

获取价格

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SN74AS74ADR TI

获取价格

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SN74AS74ADRE4 TI

获取价格

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SN74AS74ADRG4 TI

获取价格

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SN74AS74AN TI

获取价格

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SN74AS74ANE4 TI

获取价格

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SN74AS74ANSR TI

获取价格

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET