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SN74AS169ADE4

更新时间： 2024-11-14 05:17:43
品牌 Logo 应用领域
德州仪器 - TI 计数器
页数 文件大小 规格书
19页 687K
描述
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS

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SN74AS169ADE4 数据手册

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SDAS125B − MARCH 1984 − REVISED DECEMBER 1994  
SN54ALS169B, SN54AS169A . . . J PACKAGE  
SN74ALS169B, SN74AS169A . . . D OR N PACKAGE  
(TOP VIEW)  
• Fully Synchronous Operation for Counting  
and Programming  
• Internal Carry Look-Ahead Circuitry for  
Fast Counting  
U/D  
CLK  
A
V
CC  
RCO  
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15  
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• Carry Output for n-Bit Cascading  
• Fully Independent Clock Circuit  
Q
A
B
C
D
Q
B
• Package Options Include Plastic  
Small-Outline (D) Packages, Ceramic Chip  
Carriers (FK), and Standard Plastic (N) and  
Ceramic (J) 300-mil DIPs  
Q
C
Q
D
ENT  
ENP  
GND  
LOAD  
description  
SN54ALS169B, SN54AS169A . . . FK PACKAGE  
(TOP VIEW)  
These synchronous 4-bit up/down binary  
presettable counters feature an internal carry  
look-ahead circuitry for cascading in high-speed  
counting applications. Synchronous operation is  
provided by having all flip-flops clocked  
simultaneously so that the outputs change  
coincident with each other when so instructed by  
the count-enable (ENP, ENT) inputs and internal  
gating. This mode of operation eliminates the  
output counting spikes normally associated with  
asynchronous (ripple-clock) counters. A buffered  
clock (CLK) input triggers the four flip-flops on the  
rising (positive-going) edge of the clock waveform.  
3
2
1
20 19  
18  
A
B
Q
Q
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5
6
7
8
A
B
17  
16  
15  
14  
NC  
C
NC  
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Q
C
D
D
9 10 11 12 13  
These counters are fully programmable; that is,  
they may be preset to either level. The load-input  
circuitry allows loading with the carry-enable  
output of cascaded counters. Because loading is  
synchronous, setting up a low level at the load  
(LOAD) input disables the counter and causes the  
outputs to agree with the data inputs after the next  
clock pulse.  
NC − No internal connection  
The internal carry look-ahead circuitry provides for cascading counters for n-bit synchronous application without  
additional gating. ENP and ENT inputs and a ripple-carry output (RCO) are instrumental in accomplishing this  
function. Both ENP and ENT must be low to count. The direction of the count is determined by the level of the  
up/down (U/D) input. When U/D is high, the counter counts up; when low, it counts down. ENT is fed forward  
to enable RCO. RCO, thus enabled, produces a low-level pulse while the count is zero (all inputs low) counting  
down or maximum (15) counting up. This low-level overflow ripple-carry pulse can be used to enable successive  
cascaded stages. Transitions at ENP or ENT are allowed regardless of the level of the clock input. All inputs  
are diode clamped to minimize transmission-line effects, thereby simplifying system design.  
These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, LOAD, or U/D)  
that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function  
of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the  
stable setup and hold times.  
The SN54ALS169B and SN54AS169A are characterized for operation over the full military temperature range  
of −55°C to 125°C. The SN74ALS169B and SN74AS169A are characterized for operation from 0°C to 70°C.  
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Copyright 1994, Texas Instruments Incorporated  
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2−1  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
1234567...19

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SN74AS169ADE4 替代型号

型号 品牌 替代类型 描述 数据表
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