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SN74ALVC7805-40DL PDF预览

SN74ALVC7805-40DL

更新时间： 2024-11-25 15:52:07
品牌 Logo 应用领域
德州仪器 - TI 时钟先进先出芯片光电二极管内存集成电路
页数 文件大小 规格书
18页 411K
描述
256 x 18 3.3-V synchronous FIFO memory 56-SSOP 0 to 70

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SN74ALVC7805-40DL 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SSOP
包装说明：SSOP, SSOP56,.4针数：56
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.32.00.71Factory Lead Time：1 week
风险等级：5.49最长访问时间：20 ns
最大时钟频率 (fCLK)：25 MHz周期时间：40 ns
JESD-30 代码：R-PDSO-G56JESD-609代码：e4
长度：18.415 mm内存密度：4608 bit
内存集成电路类型：OTHER FIFO内存宽度：18
湿度敏感等级：1功能数量：1
端子数量：56字数：256 words
字数代码：256工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：256X18输出特性：3-STATE
可输出：YES封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装等效代码：SSOP56,.4
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, SHRINK PITCH
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
电源：3.3 V认证状态：Not Qualified
座面最大高度：2.79 mm子类别：FIFOs
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.635 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7.5 mm
Base Number Matches：1

SN74ALVC7805-40DL 数据手册

 浏览型号SN74ALVC7805-40DL的Datasheet PDF文件第2页浏览型号SN74ALVC7805-40DL的Datasheet PDF文件第3页浏览型号SN74ALVC7805-40DL的Datasheet PDF文件第4页浏览型号SN74ALVC7805-40DL的Datasheet PDF文件第5页浏览型号SN74ALVC7805-40DL的Datasheet PDF文件第6页浏览型号SN74ALVC7805-40DL的Datasheet PDF文件第7页 
SN74ALVC7805  
256 × 18  
LOW-POWER CLOCKED FIRST-IN, FIRST-OUT MEMORY  
SCAS593A – OCTOBER 1997 – REVISED APRIL 1998  
DL PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments  
Widebus Family  
Low-Power Advanced CMOS Technology  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
RESET  
D17  
D16  
D15  
D14  
D13  
D12  
D11  
OE1  
Q17  
Q16  
Q15  
GND  
Q14  
Operates From 3-V to 3.6-V V  
CC  
Free-Running Read and Write Clocks Can  
Be Asynchronous or Coincident  
2
3
4
5
Read and Write Operations Synchronized  
to Independent System Clocks  
6
7
V
CC  
Half-Full Flag and Programmable  
Almost-Full/Almost-Empty Flag  
8
Q13  
Q12  
Q11  
Q10  
Q9  
9
D10  
Bidirectional Configuration and Width  
Expansion Without Additional Logic  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
V
CC  
D9  
Input-Ready Flag Synchronized to Write  
Clock  
D8  
GND  
D7  
GND  
Q8  
Output-Ready Flag Synchronized to Read  
Clock  
D6  
Q7  
D5  
Q6  
Fast Access Times of 13 ns With a 50-pF  
Load and All Data Outputs Switching  
Simultaneously  
D4  
Q5  
D3  
V
CC  
D2  
Q4  
Data Rates up to 50 MHz  
D1  
Q3  
Pin-to-Pin Compatible With SN74ACT7803,  
SN74ACT7805, and SN74ACT7813  
D0  
Q2  
HF  
GND  
Q1  
Packaged in Shrink Small-Outline 300-mil  
Package Using 25-mil Center-to-Center  
Lead Spacing  
PEN  
AF/AE  
WRTCLK  
WRTEN2  
WRTEN1  
IR  
Q0  
RDCLK  
RDEN  
OE2  
OR  
description  
The SN74ALVC7805 is suited for buffering  
asynchronous data paths up to 50-MHz clock  
rates and 13-ns access times. This device is  
designed for 3-V to 3.6-V V  
operation. Two  
CC  
devices can be configured for bidirectional data  
buffering without additional logic.  
The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident.  
Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2 is low, and input  
ready (IR) is high. Data is read from memory on the rising edge of RDCLK when RDEN, OE1, and OE2 are low  
and output ready (OR) is high. The first word written to memory is clocked through to the output buffer,  
regardless of the RDEN, OE1, and OE2 levels. The OR flag indicates that valid data is present on the output  
buffer.  
The FIFO can be reset asynchronously to WRTCLK and RDCLK. Reset (RESET) must be asserted while at  
least four WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO  
initializes the IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO  
must be reset upon power up.  
The SN74ALVC7805 is characterized for operation from 0°C to 70°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments Incorporated.  
Copyright 1998, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...18

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SN74ALVC7805-40DL 替代型号

型号 品牌 替代类型 描述 数据表
SN74ALVC7806-40DLR TI

完全替代

 256X18 OTHER FIFO, 20ns, PDSO56, 0.300 INCH, 0.635 MM PITCH, GREEN, PLASTIC, SSOP-56
SN74ALVC7805-25DL TI

类似代替

 256 x 18 3.3-V synchronous FIFO memory 56-SSOP 0 to 70

与SN74ALVC7805-40DL相关器件

型号 品牌 获取价格 描述 数据表
SN74ALVC7805DL TI

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 		256 】 18 LOW-POWER CLOCKED FIRST-IN, FIRST-OU
SN74ALVC7805DLR TI

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 		256X18 BI-DIRECTIONAL FIFO, 20ns, PDSO56
SN74ALVC7806 TI

获取价格

 		256 】 18 LOW-POWER FIRST-IN, FIRST-OUT MEMORY
SN74ALVC7806-20DL TI

获取价格

 		256X18 OTHER FIFO, PDSO56
SN74ALVC7806-25DL TI

获取价格

 		256 】 18 LOW-POWER FIRST-IN, FIRST-OUT MEMORY
SN74ALVC7806-25DLR TI

获取价格

 		256 X 18 OTHER FIFO, 18 ns, PDSO56, 0.300 INCH, 0.635 MM PITCH, GREEN, PLASTIC, SSOP-56
SN74ALVC7806-40DL TI

获取价格

 		256 】 18 LOW-POWER FIRST-IN, FIRST-OUT MEMORY
SN74ALVC7806-40DLR TI

获取价格

 		256X18 OTHER FIFO, 20ns, PDSO56, 0.300 INCH, 0.635 MM PITCH, GREEN, PLASTIC, SSOP-56
SN74ALVC7806DL TI

获取价格

 		256 】 18 LOW-POWER FIRST-IN, FIRST-OUT MEMORY
SN74ALVC7813 TI

获取价格

 		64 】 18 LOW-POWER CLOCKED FIRST-IN, FIRST-OUT

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