Datasheet > SN74ALVC3651-20PQ

SN74ALVC3651-20PQ

更新时间： 2024-11-25 19:45:43

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SN74ALVC3651

2048 × 36

SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY

SDMS025A – OCTOBER 1999 – REVISED DECEMBER 1999

Free-Running CLKA and CLKB Can Be

Asynchronous or Coincident

Output-Ready and AE Flags Synchronized

by CLKB

Clocked FIFO Buffering Data From Port A

to Port B

Low-Power 0.8-µm Advanced CMOS

Technology

Synchronous Read-Retransmit Capability

Mailbox Register in Each Direction

Supports Clock Frequencies up to 100 MHz

Fast Access Times of 6.5 ns

Programmable Almost-Full (AF) and

Almost-Empty (AE) Flags

Pin-to-Pin Compatible With 5-V Operating

SN74ACT3631, SN74ACT3641, and

SN74ACT3651

Microprocessor Interface Control Logic

Package Options Include 120-Pin Thin

Quad Flat (PCB) and 132-Pin Plastic Quad

Flat (PQ) Packages

Input-Ready and AF Flags Synchronized by

CLKA

description

The SN74ALVC3651 is a high-speed, low-power, CMOS, synchronous FIFO memory that supports clock

frequencies up to 100 MHz and has read access times as fast as 6.5 ns. The 2048 × 36 dual-port SRAM FIFO

buffers data from port A to port B. The FIFO memory has retransmit capability, which allows previously read data

to be accessed again. The FIFO has flags to indicate empty and full conditions and two programmable flags

(almostfullandalmostempty)toindicatewhenaselectednumberofwordsisstoredinmemory.Communication

between each port takes place with two 36-bit mailbox registers. Each mailbox register has a flag that signals

when new mail has been stored. Two or more devices are used in parallel to create wider data paths. Expansion

also is possible in word depth.

The SN74ALVC3651 is a synchronous FIFO, which means each port employs a synchronous interface. All data

transfersthroughaportaregatedtothelow-to-hightransitionofacontinuous(free-running)portclockbyenable

signals. The continuous clocks for each port are independent of one another and can be asynchronous or

coincident. The enables for each port are arranged to provide a simple interface between microprocessors

and/or buses with synchronous control.

The input-ready (IR) flag and almost-full (AF) flag of the FIFO are two-stage, synchronized to CLKA. The

output-ready (OR) flag and almost-empty (AE) flag of the FIFO are two-stage, synchronized to CLKB. Offset

values for AF and AE are programmed from port A or through a serial input.

The SN74ALVC3651 is characterized for operation from 0°C to 70°C.

For more information on this device family, see the following application reports:

FIFO Patented Synchronous Retransmit: Programmable DSP-Interface Application for FIR Filtering

(literature number SCAA009)

FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control

(literature number SCAA007)

Metastability Performance of Clocked FIFOs (literature number SCZA004)

FIFO Architecture, Functions, and Applications (literature number SCAA042)

Optimizing DSP-Based Digital Filters With Application-Specific FIFOs (literature number SCAA021)

FIFO Memories: Surface-Mount Packages for PCMCIA Applications (literature number SDMA001A)

Interfacing TI Clocked FIFOs with TI Floating-Point DSPs (literature number SCAA005A)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...26

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与SN74ALVC3651-20PQ相关器件

型号	品牌	获取价格	描述	数据表
SN74ALVC3651-20PQR	TI	获取价格	2KX36 OTHER FIFO, 11.5ns, PQFP132, PLASTIC, BQFP-132
SN74ALVC3651PCB	TI	获取价格	2048 】 36 SYNCHRONOUS FIRST-IN, FIRST-OUT MEM
SN74ALVC3651PQ	TI	获取价格	2048 】 36 SYNCHRONOUS FIRST-IN, FIRST-OUT MEM
SN74ALVC74	TI	获取价格	DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
SN74ALVC74D	TI	获取价格	DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
SN74ALVC74DGV	TI	获取价格	DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
SN74ALVC74DGVR	TI	获取价格	ALVC/VCX/A SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14,
SN74ALVC74DR	TI	获取价格	ALVC/VCX/A SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14,
SN74ALVC74PW	TI	获取价格	DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
SN74ALVC74PWLE	TI	获取价格	暂无描述

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