Datasheet > SN74ALS845

SN74ALS845

更新时间： 2024-11-28 23:06:15

品牌	Logo	应用领域
德州仪器 - TI		锁存器输出元件
页数	文件大小	规格书
6页	95K
描述
8-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS

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SN74ALS845 数据手册

SN74ALS845

8-BIT BUS-INTERFACE D-TYPE LATCH

WITH 3-STATE OUTPUTS

SDAS233A – DECEMBER 1983 – REVISED JANUARY 1995

DW OR NT PACKAGE

(TOP VIEW)

• 3-State Buffer-Type Outputs Drive Bus

Lines Directly

• Bus-Structured Pinout

• Provides Extra Bus-Driving Latches

Necessary for Wider Address/Data Paths or

Buses With Parity

OE1

OE2

23 OE3

22 1Q

21 2Q

20 3Q

19 4Q

18 5Q

17 6Q

16 7Q

15 8Q

14 PRE

13 LE

• Buffered Control Inputs to Reduce

dc Loading Effects

• Power-Up High-Impedance State

• Package Options Include Plastic

Small-Outline (DW) Packages and Standard

Plastic (NT) 300-mil DIPs

8D 10

CLR 11

GND 12

description

This 8-bit latch features 3-state outputs designed

specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable

for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The eight latches are transparent D-type latches. The device has noninverting data (D) inputs and provides true

data at its outputs.

Because the clear (CLR) and preset (PRE) inputs are independent of the clock (CLK) input, taking CLR low

causes the eight Q outputs to go low. Taking PRE low causes the eight Q outputs to go high. When both PRE

and CLR are taken low, the outputs follow the preset condition.

The buffered output-enable (OE1, OE2, and OE3) inputs can be used to place the eight outputs in either a

normal logic state (high or low levels) or a high-impedance state. In the high-impedance state, the outputs

neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the

capability to drive bus lines without interface or pullup components.

The output enables do not affect the internal operation of the latches. Previously stored data can be retained

or new data can be entered while the outputs are in the high-impedance state.

The -1 version of the SN74ALS845 is identical to the standard version, except that the recommended maximum

for the -1 version is increased to 48 mA.

The SN74ALS845 is characterized for operation from 0°C to 70°C.

FUNCTION TABLE

INPUTS

OUTPUT

PRE

CLR

OE1

OE2

OE3

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6

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与SN74ALS845相关器件

型号	品牌	获取价格	描述	数据表
SN74ALS845-1DW	TI	获取价格	ALS SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO24, PLASTIC, SO-24
SN74ALS845-1DW3	TI	获取价格	IC IC,LATCH,SINGLE,8-BIT,ALS-TTL,SOP,24PIN,PLASTIC, FF/Latch
SN74ALS845-1DWP3	TI	获取价格	IC IC,LATCH,SINGLE,8-BIT,ALS-TTL,SOP,24PIN,PLASTIC, FF/Latch
SN74ALS845-1DWR	TI	获取价格	ALS SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO24, PLASTIC, SO-24
SN74ALS845-1FN	TI	获取价格	IC ALS SERIES, 8-BIT DRIVER, TRUE OUTPUT, PQCC28, Bus Driver/Transceiver
SN74ALS845-1FN3	TI	获取价格	ALS SERIES, 8-BIT DRIVER, TRUE OUTPUT, PQCC28
SN74ALS845-1NT3	TI	获取价格	ALS SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDIP24
SN74ALS845-1NTP3	TI	获取价格	IC IC,LATCH,SINGLE,8-BIT,ALS-TTL,DIP,24PIN,PLASTIC, FF/Latch
SN74ALS845DW	TI	获取价格	8-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS
SN74ALS845DW3	TI	获取价格	IC IC,LATCH,SINGLE,8-BIT,ALS-TTL,SOP,24PIN,PLASTIC, FF/Latch

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