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SN74ALS845NT-10 PDF预览

SN74ALS845NT-10

更新时间: 2024-11-29 14:35:59
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
9页 218K
描述
ALS SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDIP24

SN74ALS845NT-10 技术参数

生命周期:ObsoleteReach Compliance Code:unknown
风险等级:5.72Is Samacsys:N
其他特性:WITH TRIPLE OUTPUT ENABLE; WITH CLEAR AND PRESET系列:ALS
JESD-30 代码:R-PDIP-T24长度:31.64 mm
逻辑集成电路类型:BUS DRIVER位数:8
功能数量:1端口数量:2
端子数量:24最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE认证状态:Not Qualified
座面最大高度:5.08 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:COMMERCIAL端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
宽度:7.62 mmBase Number Matches:1

SN74ALS845NT-10 数据手册

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ꢀꢁ ꢂꢃ ꢄꢅ ꢀꢆ ꢃꢇ  
ꢆ ꢈꢉꢊ ꢋꢌ ꢉꢍꢀ ꢈꢊꢁꢋ ꢎꢏ ꢐꢄꢑꢎ ꢌꢒꢈꢋ ꢓꢔ ꢎ ꢌꢅ ꢄꢋꢑ ꢕ  
ꢖ ꢊꢋ ꢕꢌ ꢗ ꢈꢀꢋꢄꢋ ꢎꢌ ꢘꢍ ꢋꢔ ꢍꢋ ꢀ  
SDAS233A − DECEMBER 1983 − REVISED JANUARY 1995  
DW OR NT PACKAGE  
(TOP VIEW)  
3-State Buffer-Type Outputs Drive Bus  
Lines Directly  
Bus-Structured Pinout  
OE1  
OE2  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
V
CC  
1
2
3
4
5
6
7
8
9
24  
Provides Extra Bus-Driving Latches  
Necessary for Wider Address/Data Paths or  
Buses With Parity  
23 OE3  
22 1Q  
21 2Q  
20 3Q  
19 4Q  
18 5Q  
17 6Q  
16 7Q  
15 8Q  
14 PRE  
13 LE  
Buffered Control Inputs to Reduce  
dc Loading Effects  
Power-Up High-Impedance State  
Package Options Include Plastic  
Small-Outline (DW) Packages and Standard  
Plastic (NT) 300-mil DIPs  
8D 10  
CLR 11  
GND 12  
description  
This 8-bit latch features 3-state outputs designed  
specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable  
for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.  
The eight latches are transparent D-type latches. The device has noninverting data (D) inputs and provides true  
data at its outputs.  
Because the clear (CLR) and preset (PRE) inputs are independent of the clock (CLK) input, taking CLR low  
causes the eight Q outputs to go low. Taking PRE low causes the eight Q outputs to go high. When both PRE  
and CLR are taken low, the outputs follow the preset condition.  
The buffered output-enable (OE1, OE2, and OE3) inputs can be used to place the eight outputs in either a  
normal logic state (high or low levels) or a high-impedance state. In the high-impedance state, the outputs  
neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the  
capability to drive bus lines without interface or pullup components.  
The output enables do not affect the internal operation of the latches. Previously stored data can be retained  
or new data can be entered while the outputs are in the high-impedance state.  
The -1 version of the SN74ALS845 is identical to the standard version, except that the recommended maximum  
I
for the -1 version is increased to 48 mA.  
OL  
The SN74ALS845 is characterized for operation from 0°C to 70°C.  
FUNCTION TABLE  
INPUTS  
OUTPUT  
Q
PRE  
L
CLR  
X
OE1  
L
OE2  
L
OE3  
L
LE  
X
D
X
X
L
H
L
H
L
L
L
L
X
H
H
L
L
L
H
H
L
L
H
H
L
L
L
H
L
H
H
H
L
L
L
Q
0
X
X
X
X
H
X
X
X
X
X
Z
X
X
X
H
X
X
Z
Z
X
X
H
X
X
ꢋꢤ  
Copyright 1995, Texas Instruments Incorporated  
ꢠ ꢤ ꢡ ꢠꢙ ꢚꢮ ꢜꢛ ꢟ ꢧꢧ ꢥꢟ ꢝ ꢟ ꢞ ꢤ ꢠ ꢤ ꢝ ꢡ ꢩ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  

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