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SN74ALS02AN3 PDF预览

SN74ALS02AN3

更新时间: 2024-09-13 22:59:15
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德州仪器 - TI 输入元件
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8页 119K
描述
QUADRUPLE 2-INPUT POSITIVE-NOR GATES

SN74ALS02AN3 技术参数

是否无铅: 含铅生命周期:Obsolete
零件包装代码:DIP包装说明:DIP,
针数:14Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.28
系列:ALSJESD-30 代码:R-PDIP-T14
长度:19.305 mm逻辑集成电路类型:NOR GATE
功能数量:4输入次数:2
端子数量:14最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE传播延迟(tpd):12 ns
认证状态:Not Qualified座面最大高度:5.08 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:TTL温度等级:COMMERCIAL
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL宽度:7.62 mm
Base Number Matches:1

SN74ALS02AN3 数据手册

 浏览型号SN74ALS02AN3的Datasheet PDF文件第2页浏览型号SN74ALS02AN3的Datasheet PDF文件第3页浏览型号SN74ALS02AN3的Datasheet PDF文件第4页浏览型号SN74ALS02AN3的Datasheet PDF文件第5页浏览型号SN74ALS02AN3的Datasheet PDF文件第6页浏览型号SN74ALS02AN3的Datasheet PDF文件第7页 
SN54ALS02A, SN54AS02, SN74ALS02A, SN74AS02  
QUADRUPLE 2-INPUT POSITIVE-NOR GATES  
SDAS111B – APRIL 1982 – REVISED DECEMBER 1994  
SN54ALS02A, SN54AS02 . . . J PACKAGE  
SN74ALS02A, SN74AS02 . . . D OR N PACKAGE  
(TOP VIEW)  
Package Options Include Plastic  
Small-Outline (D) Packages, Ceramic Chip  
Carriers (FK), and Standard Plastic (N) and  
Ceramic (J) 300-mil DIPs  
1Y  
1A  
1B  
2Y  
2A  
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
4Y  
4B  
4A  
3Y  
3B  
3A  
description  
These devices contain four independent 2-input  
positive-NOR gates. They perform the Boolean  
functions Y = A + B or Y = A B in positive logic.  
2B  
GND  
8
The SN54ALS02A and SN54AS02 are  
characterized for operation over the full military  
temperature range of 55°C to 125°C. The  
SN74ALS02A and SN74AS02 are characterized  
for operation from 0°C to 70°C.  
SN54ALS02A, SN54AS02 . . . FK PACKAGE  
(TOP VIEW)  
FUNCTION TABLE  
(each gate)  
3
2
1
20 19  
18  
1B  
NC  
2Y  
4B  
NC  
4A  
NC  
3Y  
4
5
6
7
8
INPUTS  
OUTPUT  
Y
17  
16  
15  
14  
A
B
X
H
L
H
X
L
L
L
NC  
2A  
9 10 11 12 13  
H
NC – No internal connection  
logic symbol  
logic diagram (positive logic)  
2
1A  
3
2
1A  
3
1
4
1  
1
4
1Y  
2Y  
3Y  
4Y  
1Y  
2Y  
3Y  
4Y  
1B  
5
1B  
5
2A  
6
2A  
6
2B  
8
2B  
8
3A  
9
10  
13  
3A  
9
10  
13  
3B  
11  
3B  
11  
4A  
12  
4B  
4A  
12  
4B  
This symbol is in accordance with ANSI/IEEE Std 91-1984 and  
IEC Publication 617-12.  
Pin numbers shown are for the D, J, and N packages.  
Copyright 1994, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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