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SN74AHCT138-EP PDF预览

SN74AHCT138-EP

更新时间： 2024-11-21 02:58:43
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德州仪器 - TI /
页数 文件大小 规格书
20页 663K
描述
3-LINE TO 8-LINE DECODER/DEMULTIPLEXER

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SN74AHCT138-EP 数据手册

 浏览型号SN74AHCT138-EP的Datasheet PDF文件第2页浏览型号SN74AHCT138-EP的Datasheet PDF文件第3页浏览型号SN74AHCT138-EP的Datasheet PDF文件第4页浏览型号SN74AHCT138-EP的Datasheet PDF文件第5页浏览型号SN74AHCT138-EP的Datasheet PDF文件第6页浏览型号SN74AHCT138-EP的Datasheet PDF文件第7页 
SN54AHCT138, SN74AHCT138  
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS  
SCLS266M – DECEMBER 1995 – REVISED JULY 2003  
Inputs Are TTL-Voltage Compatible  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
Designed Specifically for High-Speed  
Memory Decoders and Data-Transmission  
Systems  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
Incorporate Three Enable Inputs to Simplify  
Cascading and/or Data Reception  
– 1000-V Charged-Device Model (C101)  
SN74AHCT138 . . . RGY PACKAGE  
(TOP VIEW)  
SN54AHCT138 . . . FK PACKAGE  
(TOP VIEW)  
SN54AHCT138 . . . J OR W PACKAGE  
SN74AHCT138 . . . D, DB, DGV, N, NS,  
OR PW PACKAGE  
(TOP VIEW)  
1
16  
A
B
V
CC  
15 Y0  
1
2
3
4
5
6
7
8
16  
3
2
1
20 19  
18  
Y1  
C
G2A  
NC  
4
5
6
7
8
B
C
G2A  
G2B  
G1  
15  
14  
13  
12  
11  
10  
2
3
4
5
6
7
Y0  
Y1  
Y2  
Y3  
Y4  
Y5  
17 Y2  
16  
14  
13  
12  
11  
10  
9
C
Y1  
Y2  
Y3  
Y4  
Y5  
Y6  
NC  
G2A  
G2B  
G1  
15  
Y3  
G2B  
G1  
14  
Y4  
9 10 11 12 13  
Y7  
Y7  
8
9
GND  
NC – No internal connection  
description/ordering information  
The ’AHCT138 3-line to 8-line decoders/demultiplexers are designed to be used in high-performance  
memory-decoding and data-routing applications that require very short propagation-delay times. In  
high-performance memory systems, this decoder can be used to minimize the effects of system decoding.  
When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and  
the enable time of the memory usually are less than the typical access time of the memory. This means that  
the effective system delay introduced by the decoder is negligible.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
QFN – RGY  
PDIP – N  
Tape and reel  
Tube  
SN74AHCT138RGYR  
SN74AHCT138N  
SN74AHCT138D  
SN74AHCT138DR  
HB138  
SN74AHCT138N  
Tube  
SOIC – D  
AHCT138  
Tape and reel  
–40°C to 85°C  
SOP – NS  
Tape and reel  
Tape and reel  
Tube  
SN74AHCT138NSR  
SN74AHCT138DBR  
SN74AHCT138PW  
SN74AHCT138PWR  
SN74AHCT138DGVR  
SNJ54AHCT138J  
AHCT138  
HB138  
SSOP – DB  
TSSOP – PW  
HB138  
Tape and reel  
Tape and reel  
Tube  
TVSOP – DGV  
CDIP – J  
HB138  
SNJ54AHCT138J  
SNJ54AHCT138W  
SNJ54AHCT138FK  
–55°C to 125°C  
CFP – W  
Tube  
SNJ54AHCT138W  
SNJ54AHCT138FK  
LCCC – FK  
Tube  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines  
are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...20

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