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SN74AHCT138QDRG4Q1 PDF预览

SN74AHCT138QDRG4Q1

更新时间: 2024-11-24 11:58:43
品牌 Logo 应用领域
德州仪器 - TI 解复用器
页数 文件大小 规格书
12页 275K
描述
3-LINE TO 8-LINE DECODER/DEMULTIPLEXER

SN74AHCT138QDRG4Q1 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP16,.25针数:16
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.61
其他特性:3 ENABLE INPUTS系列:AHCT/VHCT/VT
输入调节:STANDARDJESD-30 代码:R-PDSO-G16
JESD-609代码:e4长度:9.9 mm
负载电容(CL):50 pF逻辑集成电路类型:OTHER DECODER/DRIVER
最大I(ol):0.008 A湿度敏感等级:1
功能数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:INVERTED
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:5 V
Prop。Delay @ Nom-Sup:13 ns传播延迟(tpd):13 ns
认证状态:Not Qualified筛选级别:AEC-Q100
座面最大高度:1.75 mm子类别:Decoder/Drivers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3.9 mm
Base Number Matches:1

SN74AHCT138QDRG4Q1 数据手册

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ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢊꢋ ꢌ ꢋꢈ  
ꢉ ꢌꢍ ꢎꢁꢏ ꢇ ꢐ ꢊ ꢌꢍ ꢎꢁꢏ ꢑꢏ ꢆꢐꢑ ꢏꢒꢓ ꢑꢏꢔ ꢕꢍꢇꢎ ꢖ ꢍꢏ ꢗꢏ ꢒ  
SGDS022A − FEBRUARY 2002 − REVISED APRIL 2008  
D OR PW PACKAGE  
(TOP VIEW)  
D
D
Qualified for Automotive Applications  
EPIC(Enhanced-Performance Implanted  
CMOS) Process  
A
B
V
CC  
15 Y0  
1
2
3
4
5
6
7
8
16  
D
Inputs Are TTL-Voltage Compatible  
14  
D
Designed Specifically for High-Speed  
Memory Decoders and Data-Transmission  
Systems  
C
Y1  
13  
12  
11  
10  
9
G2A  
G2B  
G1  
Y2  
Y3  
Y4  
Y5  
Y6  
D
D
D
Incorporates Three Enable Inputs to  
Simplify Cascading and/or Data Reception  
Y7  
GND  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
ESD Protection Exceeds 2000 V Per  
MIL-STD-833, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
description  
The SN74AHCT138Q 3-line to 8-line decoder/demultiplexer is designed to be used in high-performance  
memory-decoding and data-routing applications that require very short propagation-delay times. In  
high-performance memory systems, this decoder can be used to minimize the effects of system decoding.  
When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and  
the enable time of the memory usually are less than the typical access time of the memory. This means that  
the effective system delay introduced by the decoder is negligible.  
The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two  
active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding.  
A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one  
inverter. An enable input can be used as a data input for demultiplexing applications.  
{
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
SOIC − D  
Tape and reel  
Tape and reel  
SN74AHCT138QDRQ1  
SN74AHCT138QPWRQ1  
AHCT138Q  
HB138Q  
−40°C to 125°C  
TSSOP − PW  
For the most current package and ordering information, see the Package Option Addendum at the end of this  
document, or see the TI web site at http://www.ti.com.  
Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments.  
ꢇꢣ  
Copyright 2008, Texas Instruments Incorporated  
ꢟ ꢣ ꢠ ꢟꢘ ꢙꢭ ꢛꢚ ꢞ ꢦꢦ ꢤꢞ ꢜ ꢞ ꢝ ꢣ ꢟ ꢣ ꢜ ꢠ ꢨ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74AHCT138QDRG4Q1 替代型号

型号 品牌 替代类型 描述 数据表
SN74AHCT138QDRQ1 TI

完全替代

汽车类 3 线至 8 线解码器/多路解复用器 | D | 16 | -40 to 125
SN74HCT138PWR TI

类似代替

3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SN74LVC138ADR TI

类似代替

3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

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