SN54AHCT123A, SN74AHCT123A
DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATORS
SCLS420E – JUNE 1998 – REVISED AUGUST 2000
SN54AHCT123A . . . J OR W PACKAGE
SN74AHCT123A . . . D, DB, DGV, N, OR PW PACKAGE
(TOP VIEW)
EPIC (Enhanced-Performance Implanted
CMOS) Process
Inputs Are TTL-Voltage Compatible
1A
1B
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
Schmitt-Trigger Circuitry On A, B, and CLR
Inputs for Slow Input Transition Rates
1R /C
ext ext
1CLR
1Q
1C
1Q
ext
Edge Triggered From Active-High or
Active-Low Gated Logic Inputs
2Q
12 2Q
Retriggerable for Very Long Output Pulses
Overriding Clear Terminates Output Pulse
11
10
9
2C
2CLR
2B
ext
2R /C
ext ext
GND
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
2A
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
SN54AHCT123A . . . FK PACKAGE
(TOP VIEW)
– 1000-V Charged-Device Model (C101)
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), and
Thin Shrink Small-Outline (PW) Packages,
Ceramic Flat (W) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) DIPs
3
2
1 20 19
18
1C
1Q
1CLR
1Q
4
5
6
7
8
ext
17
16
NC
NC
15 2Q
14
9 10 11 12 13
2Q
2CLR
2C
ext
description
These edge-triggered multivibrators feature
output pulse-duration control by three methods. In
the first method, the A input is low, and the B input
goes high. In the second method, the B input is
high, and the A input goes low. In the third method,
the A input is low, the B input is high, and the clear
(CLR) input goes high.
NC – No internal connection
Theoutputpulse durationisprogrammedbyselectingexternalresistanceandcapacitancevalues. Theexternal
timing capacitor must be connected between C and R /C (positive) and an external resistor connected
ext
ext ext
betweenR /C andV .Toobtainvariablepulsedurations,connectanexternalvariableresistancebetween
ext ext
CC
R
/C and V . The output pulse duration also can be reduced by taking CLR low.
ext ext
CC
Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input
pulse. The A, B, and CLR inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition
rates with jitter-free triggering at the outputs.
Once triggered, the basic pulse duration can be extended by retriggering the gated low-level-active (A) or
high-level-active (B) input. Pulse duration can be reduced by taking CLR low. CLR input can be used to override
A or B inputs. The input/output timing diagram illustrates pulse control by retriggering the inputs and early
clearing.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 2000, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
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