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SN74AHCT125DGV PDF预览

SN74AHCT125DGV

更新时间： 2024-11-24 23:09:43
品牌 Logo 应用领域
德州仪器 - TI 输出元件
页数 文件大小 规格书
18页 632K
描述
QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS

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SN74AHCT125DGV 技术参数

生命周期：Obsolete零件包装代码：SOIC
包装说明：TSSOP, TSSOP14,.25,16针数：14
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.82系列：AHCT/VHCT
JESD-30 代码：R-PDSO-G14长度：4.4 mm
负载电容（CL）：50 pF逻辑集成电路类型：BUS DRIVER
位数：1功能数量：4
端口数量：2端子数量：14
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP14,.25,16封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH传播延迟（tpd）：8.5 ns
认证状态：Not Qualified座面最大高度：1.2 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.4 mm
端子位置：DUAL宽度：3.6 mm

SN74AHCT125DGV 数据手册

 浏览型号SN74AHCT125DGV的Datasheet PDF文件第2页浏览型号SN74AHCT125DGV的Datasheet PDF文件第3页浏览型号SN74AHCT125DGV的Datasheet PDF文件第4页浏览型号SN74AHCT125DGV的Datasheet PDF文件第5页浏览型号SN74AHCT125DGV的Datasheet PDF文件第6页浏览型号SN74AHCT125DGV的Datasheet PDF文件第7页 
SN54AHCT125, SN74AHCT125  
QUADRUPLE BUS BUFFER GATES  
WITH 3-STATE OUTPUTS  
SCLS264O – DECEMBER 1995 – REVISED JULY 2003  
Inputs Are TTL-Voltage Compatible  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
– 1000-V Charged-Device Model (C101)  
SN54AHCT125 . . . FK PACKAGE  
(TOP VIEW)  
SN74AHCT125 . . . RGY PACKAGE  
(TOP VIEW)  
SN54AHCT125 . . . J OR W PACKAGE  
SN74AHCT125 . . . D, DB, DGV, N, NS,  
OR PW PACKAGE  
(TOP VIEW)  
1
14  
1OE  
1A  
V
CC  
13 4OE  
1
2
3
4
5
6
7
14  
3
2
1 20 19  
18  
4A  
NC  
4Y  
1Y  
NC  
1A  
1Y  
13 4OE  
12 4A  
2
3
4
5
6
4
5
6
7
8
17  
16  
12  
11  
10  
9
1Y  
4A  
2OE  
NC  
11  
10  
9
2OE  
2A  
4Y  
2OE  
2A  
4Y  
15 NC  
14  
9 10 11 12 13  
3OE  
3A  
3OE  
3A  
3OE  
2A  
2Y  
2Y  
7
8
8
GND  
3Y  
NC – No internal connection  
description/ordering information  
The ’AHCT125 devices are quadruple bus buffer gates featuring independent line drivers with 3-state outputs.  
Each output is disabled when the associated output-enable (OE) input is high. When OE is low, the respective  
gate passes the data from the A input to its Y output.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
QFN – RGY  
PDIP – N  
Tape and reel  
Tube  
SN74AHCT125RGYR  
SN74AHCT125N  
HB125  
SN74AHCT125N  
Tube  
SN74AHCT125D  
SOIC – D  
AHCT125  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SN74AHCT125DR  
SN74AHCT125NSR  
SN74AHCT125DBR  
SN74AHCT125PW  
SN74AHCT125PWR  
SN74AHCT125DGVR  
SNJ54AHCT125J  
SNJ54AHCT125W  
SNJ54AHCT125FK  
–40°C to 85°C  
SOP – NS  
AHCT125  
HB125  
SSOP – DB  
TSSOP – PW  
HB125  
Tape and reel  
Tape and reel  
Tube  
TVSOP – DGV  
CDIP – J  
HB125  
SNJ54AHCT125J  
SNJ54AHCT125W  
SNJ54AHCT125FK  
–55°C to 125°C  
CFP – W  
Tube  
LCCC – FK  
Tube  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...18

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