5秒后页面跳转
捷配首页

Datasheet > SN74ACT72221L
SN74ACT72221L PDF预览

SN74ACT72221L

更新时间： 2024-11-15 12:22:47
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
21页 327K
描述
SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES

阅读下载

中文翻译

获取价格

SN74ACT72221L 数据手册

 浏览型号SN74ACT72221L的Datasheet PDF文件第2页浏览型号SN74ACT72221L的Datasheet PDF文件第3页浏览型号SN74ACT72221L的Datasheet PDF文件第4页浏览型号SN74ACT72221L的Datasheet PDF文件第5页浏览型号SN74ACT72221L的Datasheet PDF文件第6页浏览型号SN74ACT72221L的Datasheet PDF文件第7页 
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢂ
ꢇꢇ  
ꢈ
ꢈ
ꢉ
ꢊ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢂ
ꢇ
ꢌ
ꢕ
ꢇ
ꢈ
ꢁ
ꢇ
ꢇ ×  
ꢈ
ꢉ
ꢊ
ꢀ
ꢁ
ꢈ
ꢂ
ꢎ
ꢔ
ꢃ
ꢇ
ꢀ
ꢄ
ꢅ
ꢆ
ꢍ
ꢁ
ꢂ
ꢊ
ꢊ
ꢇ
ꢇ
ꢗ
ꢇ
ꢎ
ꢘ
ꢋ
ꢃ
ꢔ
ꢈ
ꢉ
ꢊ
ꢀ
ꢍ
ꢁ
ꢊ
ꢖ
ꢂ
ꢄ
ꢆ
ꢃ
ꢁ
ꢄ
ꢐ
ꢚ
ꢅ
ꢆ
ꢂ
ꢍ
ꢕ
ꢇ
ꢇ
ꢃ
ꢈ
ꢉ
ꢍ
ꢍ
ꢊ
ꢃ
×
ꢏ
×
ꢃ
ꢎ
ꢑ
×
ꢀ
ꢒ
ꢁ
ꢅ
ꢓ
ꢔ
ꢕ
ꢖ
ꢀ
ꢗ
ꢘ
ꢆ
ꢙ
ꢘ
ꢀ
ꢆ
ꢙ
ꢕ
ꢛ
ꢚ
ꢔ
ꢘ
ꢛ
ꢀ
SCAS222 − FEBRUARY 1993 − REVISED JUNE 1993  
RJ PACKAGE  
(TOP VIEW)  
D Read and Write Clocks Can Be  
Asynchronous or Coincident  
D Organization:  
− SN74ACT72211L − 512 × 9  
− SN74ACT72221L − 1024 × 9  
− SN74ACT72231L − 2048 × 9  
− SN74ACT72241L − 4096 × 9  
4
3
2
1
32 31 30  
29  
5
D1  
D0  
PAF  
PAE  
RS  
6
7
8
9
28  
27  
26  
25  
WEN1  
WCLK  
WEN2/LD  
D Write and Read Cycle Times of 15 ns  
D Bit-Width Expandable  
GND  
V
CC  
REN1 10  
24 Q8  
D Empty and Full Flags  
RCLK  
REN2  
OE  
Q7  
Q6  
Q5  
11  
12  
13  
23  
22  
21  
D Programmable Almost-Empty and  
Almost-Full Flags With Default Offsets  
of Empty+7 and Full−7, Respectively  
14 15 16 17 18 19 20  
D TTL-Compatible Inputs  
D Fully Compatible With the  
IDT72211/72221/72231/72241  
D Available in 32-Pin Plastic J-Leaded  
Chip Carrier (RJ)  
description  
The SN74ACT72211L, SN74ACT72221L, SN74ACT72231L, and SN74ACT72241L are constructed with  
CMOS dual-port SRAM and are arranged as 512, 1024, 2048, and 4096 9-bit words, respectively. Internal write  
and read address counters provide data throughput on a first-in, first-out (FIFO) basis. Full and empty flags  
prevent memory overflow and underflow, and two programmable flags (almost full and almost empty) are  
provided.  
The SN74ACT72211L, SN74ACT72221L, SN74ACT72231L, and SN74ACT72241L are synchronous FIFOs,  
which means the data input port and data output port each employ synchronous control. Write-enable (WEN1,  
WEN2/LD) signals allow the low-to-high transition of the write clock (WCLK) to store data in memory, and  
read-enable (REN1, REN2) signals allow the low-to-high transition of the read clock (RCLK) to read data from  
memory. WCLK and RCLK are independent of one another and can operate asynchronously or be tied together  
for single-clock operation.  
The empty-flag (EF) output is synchronized to RCLK and the full-flag (FF) output is synchronized to WCLK to  
indicate absolute boundary conditions. Write operations are prohibited when FF is low, and read operations are  
prohibited when EF is low. Two programmable flags, programmable almost empty (PAE) and programmable  
almost full (PAF), can both be programmed to indicate any measure of memory fill. After reset, PAE defaults  
to empty+7 and PAF defaults to full−7. Flag-offset programming control is similar to a memory write with the  
use of the load (WEN2/LD) signal.  
These devices are suited for providing a data channel between two buses operating at asynchronous or  
synchronous rates. Applications include use as rate buffers for graphics systems and high-speed queues for  
communication systems. A 9-bit-wide data path is provided for the transmission of byte data plus a parity bit  
or packet-framing information.  
The SN74ACT72211L, SN74ACT72221L, SN74ACT72231L, and SN74ACT72241L are characterized for  
operation from 0°C to 70°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢜ
ꢜ
ꢔ
ꢕ
ꢬ
ꢐ
ꢧ
ꢖ
ꢅ
ꢥ
ꢆ
ꢦ
ꢘ
ꢠ
ꢕ
ꢞ
ꢁ
ꢟ
ꢐ
ꢄ
ꢆ
ꢄ
ꢝ
ꢞ
ꢨ
ꢟ
ꢠ
ꢦ
ꢡ
ꢢ
ꢣ
ꢣ
ꢤ
ꢤ
ꢝ
ꢝ
ꢠ
ꢠ
ꢞ
ꢞ
ꢝ
ꢥ
ꢥ
ꢩ
ꢦ
ꢧ
ꢡ
ꢡ
ꢨ
ꢨ
ꢞ
ꢤ
ꢣ
ꢢ
ꢥ
ꢥ
ꢠ
ꢟ
ꢩ
ꢆꢨ  
ꢧ
ꢪ
ꢥ
ꢫ
ꢝ
ꢦ
ꢣ
ꢥ
ꢤ
ꢝ
ꢤ
ꢠ
ꢡ
ꢞ
ꢧ
ꢬ
ꢣ
ꢞ
ꢤ
ꢤ
ꢨ
ꢥ
ꢭ
Copyright 1993, Texas Instruments Incorporated  
ꢡ
ꢠ
ꢦ
ꢤ
ꢠ
ꢡ
ꢢ
ꢤ
ꢠ
ꢥ
ꢩ
ꢝ
ꢟ
ꢝ
ꢦ
ꢨ
ꢡ
ꢤ
ꢮ
ꢤ
ꢨ
ꢡ
ꢠ
ꢟ
ꢯ
ꢣ
ꢘ
ꢞ
ꢢ
ꢨ
ꢥ
ꢤ
ꢣ
ꢞ
ꢬ
ꢣ
ꢡ
ꢬ
ꢰ
ꢣ
ꢤ ꢨ ꢥ ꢤꢝ ꢞꢲ ꢠꢟ ꢣ ꢫꢫ ꢩꢣ ꢡ ꢣ ꢢ ꢨ ꢤ ꢨ ꢡ ꢥ ꢭ  
ꢡ
ꢡ
ꢣ
ꢞ
ꢤ
ꢱ
ꢭ
ꢜ
ꢡ
ꢠ
ꢬ
ꢧ
ꢦ
ꢤ
ꢝ
ꢠ
ꢞ
ꢩ
ꢡ
ꢠ
ꢦ
ꢨ
ꢥ
ꢥ
ꢝ
ꢞ
ꢲ
ꢬ
ꢠ
ꢨ
ꢥ
ꢞ
ꢠ
ꢤ
ꢞ
ꢨ
ꢦ
ꢨ
ꢥ
ꢥ
ꢣ
ꢡ
ꢝ
ꢫ
ꢱ
ꢝ
ꢞ
ꢦ
ꢫ
ꢧ
ꢬ
ꢨ
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
1234567...21

中文翻译

下载PDF

与SN74ACT72221L相关器件

型号 品牌 获取价格 描述 数据表
SN74ACT72221L15RJ TI

获取价格

 		SYNCHRONOUS FIRST-IN FIRST-OUT MEMORIES
SN74ACT72221L-15RJR TI

获取价格

 		1KX9 OTHER FIFO, 10ns, PQCC32, PLASTIC, LCC-32
SN74ACT72221L20RJ TI

获取价格

 		1KX9 OTHER FIFO, 12ns, PQCC32, PLASTIC, LCC-32
SN74ACT72221L-20RJ TI

获取价格

 		1KX9 OTHER FIFO, 12ns, PQCC32, PLASTIC, LCC-32
SN74ACT72221L25RJ ROCHESTER

获取价格

 		1KX9 OTHER FIFO, 15ns, PQCC32, PLASTIC, LCC-32
SN74ACT72221L25RJ TI

获取价格

 		SYNCHRONOUS FIRST-IN FIRST-OUT MEMORIES
SN74ACT72221L-25RJR TI

获取价格

 		1KX9 OTHER FIFO, 15ns, PQCC32, PLASTIC, LCC-32
SN74ACT72221L35RJ TI

获取价格

 		SYNCHRONOUS FIRST-IN FIRST-OUT MEMORIES
SN74ACT72221L50RJ TI

获取价格

 		SYNCHRONOUS FIRST-IN FIRST-OUT MEMORIES
SN74ACT72221L-50RJ TI

获取价格

 		1KX9 OTHER FIFO, 25ns, PQCC32, PLASTIC, LCC-32

与SN74ACT72221L相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证