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SN74ACT72231L-20RJR PDF预览

SN74ACT72231L-20RJR

更新时间： 2024-11-15 14:35:59
品牌 Logo 应用领域
德州仪器 - TI 时钟先进先出芯片内存集成电路
页数 文件大小 规格书
21页 322K
描述
2KX9 OTHER FIFO, 12ns, PQCC32, PLASTIC, LCC-32

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SN74ACT72231L-20RJR 技术参数

是否Rohs认证：不符合生命周期：Obsolete
零件包装代码：QFJ包装说明：QCCJ, LDCC32,.5X.6
针数：32Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.32.00.71
风险等级：5.49Is Samacsys：N
最长访问时间：12 ns最大时钟频率 (fCLK)：50 MHz
周期时间：20 nsJESD-30 代码：R-PQCC-J32
JESD-609代码：e0长度：13.995 mm
内存密度：18432 bit内存集成电路类型：OTHER FIFO
内存宽度：9功能数量：1
端子数量：32字数：2048 words
字数代码：2000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：2KX9输出特性：3-STATE
可输出：YES封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装等效代码：LDCC32,.5X.6
封装形状：RECTANGULAR封装形式：CHIP CARRIER
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5 V认证状态：Not Qualified
座面最大高度：3.56 mm子类别：FIFOs
最大压摆率：0.16 mA最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：TIN LEAD
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：11.4554 mmBase Number Matches：1

SN74ACT72231L-20RJR 数据手册

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SCAS222 − FEBRUARY 1993 − REVISED JUNE 1993  
RJ PACKAGE  
(TOP VIEW)  
D Read and Write Clocks Can Be  
Asynchronous or Coincident  
D Organization:  
− SN74ACT72211L − 512 × 9  
− SN74ACT72221L − 1024 × 9  
− SN74ACT72231L − 2048 × 9  
− SN74ACT72241L − 4096 × 9  
4
3
2
1
32 31 30  
29  
5
D1  
D0  
PAF  
PAE  
RS  
6
7
8
9
28  
27  
26  
25  
WEN1  
WCLK  
WEN2/LD  
D Write and Read Cycle Times of 15 ns  
D Bit-Width Expandable  
GND  
V
CC  
REN1 10  
24 Q8  
D Empty and Full Flags  
RCLK  
REN2  
OE  
Q7  
Q6  
Q5  
11  
12  
13  
23  
22  
21  
D Programmable Almost-Empty and  
Almost-Full Flags With Default Offsets  
of Empty+7 and Full−7, Respectively  
14 15 16 17 18 19 20  
D TTL-Compatible Inputs  
D Fully Compatible With the  
IDT72211/72221/72231/72241  
D Available in 32-Pin Plastic J-Leaded  
Chip Carrier (RJ)  
description  
The SN74ACT72211L, SN74ACT72221L, SN74ACT72231L, and SN74ACT72241L are constructed with  
CMOS dual-port SRAM and are arranged as 512, 1024, 2048, and 4096 9-bit words, respectively. Internal write  
and read address counters provide data throughput on a first-in, first-out (FIFO) basis. Full and empty flags  
prevent memory overflow and underflow, and two programmable flags (almost full and almost empty) are  
provided.  
The SN74ACT72211L, SN74ACT72221L, SN74ACT72231L, and SN74ACT72241L are synchronous FIFOs,  
which means the data input port and data output port each employ synchronous control. Write-enable (WEN1,  
WEN2/LD) signals allow the low-to-high transition of the write clock (WCLK) to store data in memory, and  
read-enable (REN1, REN2) signals allow the low-to-high transition of the read clock (RCLK) to read data from  
memory. WCLK and RCLK are independent of one another and can operate asynchronously or be tied together  
for single-clock operation.  
The empty-flag (EF) output is synchronized to RCLK and the full-flag (FF) output is synchronized to WCLK to  
indicate absolute boundary conditions. Write operations are prohibited when FF is low, and read operations are  
prohibited when EF is low. Two programmable flags, programmable almost empty (PAE) and programmable  
almost full (PAF), can both be programmed to indicate any measure of memory fill. After reset, PAE defaults  
to empty+7 and PAF defaults to full−7. Flag-offset programming control is similar to a memory write with the  
use of the load (WEN2/LD) signal.  
These devices are suited for providing a data channel between two buses operating at asynchronous or  
synchronous rates. Applications include use as rate buffers for graphics systems and high-speed queues for  
communication systems. A 9-bit-wide data path is provided for the transmission of byte data plus a parity bit  
or packet-framing information.  
The SN74ACT72211L, SN74ACT72221L, SN74ACT72231L, and SN74ACT72241L are characterized for  
operation from 0°C to 70°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
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ꢥ ꢤ ꢣ ꢞꢬ ꢣ ꢡꢬ ꢰ ꢣ ꢡꢡ ꢣ ꢞ ꢤꢱꢭ ꢜꢡ ꢠ ꢬꢧꢦ ꢤꢝꢠꢞ ꢩꢡ ꢠꢦ ꢨꢥ ꢥꢝ ꢞꢲ ꢬꢠꢨ ꢥ ꢞꢠꢤ ꢞꢨ ꢦꢨ ꢥꢥ ꢣꢡ ꢝꢫ ꢱ ꢝꢞꢦ ꢫꢧꢬ ꢨ  
ꢤ ꢨ ꢥ ꢤꢝ ꢞꢲ ꢠꢟ ꢣ ꢫꢫ ꢩꢣ ꢡ ꢣ ꢢ ꢨ ꢤ ꢨ ꢡ ꢥ ꢭ  
Copyright 1993, Texas Instruments Incorporated  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
1234567...21

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