Datasheet > 存储 > FIFO> SN74ACT7200L15NP

SN74ACT7200L15NP

更新时间： 2024-11-06 05:17:59

品牌	Logo	应用领域
德州仪器 - TI		/
页数	文件大小	规格书
23页	305K
描述
256 】 9, 512 】 9, 1024 】 9 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES

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SN74ACT7200L15NP 数据手册

SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA

256 × 9, 512 × 9, 1024 × 9

ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES

SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995

DV OR NP PACKAGE

(TOP VIEW)

Reads and Writes Can Be Asynchronous

or Coincident

Organization:

– SN74ACT7200L – 256 × 9

– SN74ACT7201LA – 512 × 9

– SN74ACT7202LA – 1024 × 9

FL/RT

Fast Data Access Times of 15 ns

Read and Write Frequencies up to 40 MHz

Bit-Width and Word-Depth Expansion

XO/HF

Fully Compatible With the

IDT7200/7201/7202

Q1 10

19 Q7

Retransmit Capability

Empty, Full, and Half-Full Flags

TTL-Compatible Inputs

Q8 13

16 Q4

GND 14

Available in 28-Pin Plastic DIP (NP),

Small-Outline (DV), and 32-Pin Plastic

J-Leaded Chip-Carrier (RJ) Packages

RJ PACKAGE

(TOP VIEW)

description

The SN74ACT7200L, SN74ACT7201LA, and

SN74ACT7202LA are constructed with dual-port

SRAM and have internal write and read address

counters to provide data throughput on a first-in,

first-out (FIFO) basis. Write and read operations

are independent and can be asynchronous or

coincident. Empty and full status flags prevent

underflow and overflow of memory, and

depth-expansion logic allows combining the

storage cells of two or more devices into one

FIFO. Word-width expansion is also possible.

32 31 30

FL/RT

Q0 10

24 EF

XO/HF

14 15 16 17 18 19 20

Data is loaded into memory by the write-enable

(W) input and unloaded by the read-enable (R)

input. Read and write cycle times of 25 ns

(40 MHz) are possible with data access times of

15 ns.

NC – No internal connection

These devices are particularly suited for providing a data channel between two buses operating at

asynchronous rates. Applications include use as rate buffers from analog-to-digital converters in data-

acquisition systems, temporary storage elements between buses and magnetic or optical memories, and

queues for communication systems. A 9-bit-wide data path is provided for the transmission of byte data plus

a parity bit or packet-framing information. The read pointer can be reset independently of the write pointer for

retransmitting previously read data when a device is not used in depth expansion.

The SN74ACT7200L, SN74ACT7201LA, and SN74ACT7202LA are characterized for operation from 0°C

to 70°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...23

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与SN74ACT7200L15NP相关器件

型号	品牌	获取价格	描述	数据表
SN74ACT7200L-15NP	TI	获取价格	256X9 OTHER FIFO, 15ns, PDIP28, PLASTIC, DIP-28
SN74ACT7200L15RJ	TI	获取价格	256 】 9, 512 】 9, 1024 】 9 ASYNCHRONOUS FIRST
SN74ACT7200L15RJ	ROCHESTER	获取价格	256X9 OTHER FIFO, 15ns, PQCC32, PLASTIC, LCC-32
SN74ACT7200L-15RJ	TI	获取价格	256X9 OTHER FIFO, 15ns, PQCC32
SN74ACT7200L-15RJR	TI	获取价格	256X9 OTHER FIFO, 15ns, PQCC32
SN74ACT7200L20DV	TI	获取价格	256 】 9, 512 】 9, 1024 】 9 ASYNCHRONOUS FIRST
SN74ACT7200L20NP	TI	获取价格	256 】 9, 512 】 9, 1024 】 9 ASYNCHRONOUS FIRST
SN74ACT7200L20NP	ROCHESTER	获取价格	256 X 9 OTHER FIFO, PDIP28, PLASTIC, DIP-28
SN74ACT7200L20RJ	TI	获取价格	256 】 9, 512 】 9, 1024 】 9 ASYNCHRONOUS FIRST
SN74ACT7200L20RJ	ROCHESTER	获取价格	256 X 9 OTHER FIFO, PQCC32, PLASTIC, LCC-32

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