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SN74ACT11109DR PDF预览

SN74ACT11109DR

更新时间: 2024-11-05 15:52:03
品牌 Logo 应用领域
德州仪器 - TI 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
5页 76K
描述
ACT SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, PLASTIC, SO-16

SN74ACT11109DR 技术参数

生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP,针数:16
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.84系列:ACT
JESD-30 代码:R-PDSO-G16长度:9.9 mm
逻辑集成电路类型:J-KBAR FLIP-FLOP位数:2
功能数量:2端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE传播延迟(tpd):9.1 ns
认证状态:Not Qualified座面最大高度:1.75 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL触发器类型:POSITIVE EDGE
宽度:3.9 mm最小 fmax:100 MHz
Base Number Matches:1

SN74ACT11109DR 数据手册

 浏览型号SN74ACT11109DR的Datasheet PDF文件第2页浏览型号SN74ACT11109DR的Datasheet PDF文件第3页浏览型号SN74ACT11109DR的Datasheet PDF文件第4页浏览型号SN74ACT11109DR的Datasheet PDF文件第5页 
ꢀ ꢁ ꢂꢃꢄ ꢅꢅꢅ ꢆ ꢇ ꢈꢉ ꢊ ꢁ ꢂꢃ ꢄꢅꢅꢅꢆ ꢇ  
ꢋꢌꢂ ꢍꢉꢎ ꢏꢐ ꢉꢑ ꢒ ꢓꢔꢄ ꢔ ꢕꢖꢏꢖꢋ ꢗꢖ ꢏꢄꢘ ꢔꢗ ꢗ ꢖꢘ ꢖꢋꢉꢙ ꢍ ꢔꢑ ꢏ ꢙꢍꢒ ꢑ ꢓ  
ꢚ ꢔꢄ ꢛꢉ ꢃꢍꢖ ꢂꢘꢉꢂꢜꢋꢉ ꢑ ꢘꢖ ꢓ ꢖꢄ  
SCAS451 − FEBRUARY 1987 − REVISED APRIL 1993  
54ACT11109 . . . J PACKAGE  
74ACT11109 . . . D OR N PACKAGE  
(TOP VIEW)  
Inputs Are TTL-Voltage Compatible  
Flow-Through Architecture Optimizes  
PCB Layout  
Center-Pin V  
and GND Configurations  
Minimize High-Speed Switching Noise  
1CLK  
1K  
1J  
1PRE  
1Q  
1Q  
GND  
2Q  
2Q  
2PRE  
2CLK  
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
EPIC(Enhanced-Performance Implanted  
1CLR  
CMOS) 1-µm Process  
V
CC  
500-mA Typical Latch-Up Immunity  
at 125°C  
Package Options Include Plastic  
Small-Outline Packages, Ceramic Chip  
Carriers, and Standard Plastic and  
Ceramic 300-mil DIPs  
2CLR  
2J  
2K  
54ACT11109 . . . FK PACKAGE  
(TOP VIEW)  
description  
These devices contain two independent J-K  
positive-edge-triggered flip-flops. A low level at  
the preset (1PRE or 2PRE) or clear (1CLR or  
2CLR) input sets or resets the outputs regardless  
of the levels of the other inputs. When PRE and  
CLR are inactive (high), data at the J and K inputs  
meeting the setup time requirements are  
transferred to the outputs on the positive-going  
edge of the clock pulse. Clock triggering occurs at  
a voltage level and is not directly related to the rise  
time of the clock pulse. Following the hold-time  
interval, data at the J and K inputs may be  
changed without affecting the levels at the  
outputs. These versatile flip-flops can perform as  
toggle flip-flops by grounding K and tying J high.  
They also can perform as D-type flip-flops if J and  
K are tied together.  
3
2
1
20 19  
18  
2J  
1K  
4
5
6
7
8
2K  
1CLK  
NC  
17  
16  
15  
14  
NC  
2CLK  
2PRE  
1PRE  
1Q  
9 10 11 12 13  
NC − No internal connection  
The 54ACT11109 is characterized for operation over the full military temperature range of 55°C to 125°C. The  
74ACT11109 is characterized for operation from 40°C to 85°C.  
FUNCTION TABLE  
INPUTS  
OUTPUTS  
PRE  
L
CLR  
H
CLK  
X
J
X
X
X
L
K
X
X
X
L
Q
H
L
Q
L
H
L
X
H
H
L
L
X
H
H
H
L
H
H
H
H
L
L
Toggle  
H
H
H
H
X
Q
Q
0
0
H
H
H
X
H
L
H
H
L
Q
0
Q
0
This configuration is nonstable; that is, it will not persist when  
either PRE or CLR returns to the inactive (high) level.  
EPIC is a trademark of Texas Instruments Incorporated.  
ꢄꢪ  
Copyright 1993, Texas Instruments Incorporated  
ꢦ ꢪ ꢧ ꢦꢟ ꢠꢴ ꢢꢡ ꢥ ꢭꢭ ꢫꢥ ꢣ ꢥ ꢤ ꢪ ꢦ ꢪ ꢣ ꢧ ꢯ  
2−1  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77001  

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