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SN74ACT11244DW PDF预览

SN74ACT11244DW

更新时间: 2024-11-05 13:13:47
品牌 Logo 应用领域
德州仪器 - TI 驱动器输出元件
页数 文件大小 规格书
14页 625K
描述
ACT SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, PDSO24

SN74ACT11244DW 技术参数

生命周期:Obsolete包装说明:SOP,
Reach Compliance Code:unknown风险等级:5.59
系列:ACTJESD-30 代码:R-PDSO-G24
长度:15.4 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER位数:4
功能数量:2端口数量:2
端子数量:24最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE传播延迟(tpd):9.2 ns
认证状态:Not Qualified座面最大高度:2.65 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:7.5 mm
Base Number Matches:1

SN74ACT11244DW 数据手册

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74ACT11244  
OCTAL BUFFER/LINE DRIVER  
WITH 3-STATE OUTPUTS  
SCAS006C − AUGUST 1987 − REVISED APRIL 1996  
DB, DW, NT, OR PW PACKAGE  
(TOP VIEW)  
D
3-State Outputs Drive Bus Lines or Buffer  
Memory Address Registers  
D
D
Inputs Are TTL-Voltage Compatible  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
1Y1  
1Y2  
1Y3  
1OE  
1A1  
1A2  
1A3  
1A4  
VCC  
VCC  
2A1  
2A2  
2A3  
2A4  
2OE  
Flow-Through Architecture Optimizes  
PCB Layout  
2
3
D
D
D
D
Center-Pin V and GND Configurations to  
4
1Y4  
CC  
Minimize High-Speed Switching Noise  
5
GND  
GND  
GND  
GND  
2Y1  
2Y2  
2Y3  
2Y4  
6
EPICt (Enhanced-Performance Implanted  
CMOS) 1-mm Process  
7
8
500-mA Typical Latch-Up Immunity at  
125°C  
Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
Packages, and Standard Plastic 300-mil  
DIPs (NT)  
9
10  
11  
12  
description  
ThIs octal buffer or line driver is designed specifically to improve both the performance and density of 3-state  
memory address drivers, clock drivers, and bus-oriented receivers and transmitters. Together with the  
’ACT11240, this device provides the choice of various combinations of inverting and noninverting outputs.  
The 74ACT11244 is characterized for operation from −40°C to 85°C.  
FUNCTION TABLE  
OUTPUT  
DATA  
OUTPUT  
Y
ENABLE  
INPUT  
A
1OE, 2OE  
H
L
L
X
L
Z
L
H
H
logic symbol†  
24  
13  
1OE  
2OE  
EN  
20  
EN  
23  
1A1  
22  
1
2
3
4
17  
16  
15  
14  
9
10  
11  
12  
1Y1  
1Y2  
1Y3  
1Y4  
2A1  
2A2  
2A3  
2A4  
2Y1  
2Y2  
2Y3  
2Y4  
1A2  
21  
1A3  
20  
1A4  
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright © 1996, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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