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SN74ACT11478DW PDF预览

SN74ACT11478DW

更新时间： 2024-11-05 14:27:03
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
5页 89K
描述
ACT SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO24, PLASTIC, SOIC-24

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SN74ACT11478DW 技术参数

生命周期：Obsolete零件包装代码：SOIC
包装说明：SOP,针数：24
Reach Compliance Code：unknown风险等级：5.73
系列：ACTJESD-30 代码：R-PDSO-G24
长度：15.4 mm逻辑集成电路类型：BUS DRIVER
位数：8功能数量：1
端口数量：2端子数量：24
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
传播延迟（tpd）：14.2 ns认证状态：Not Qualified
座面最大高度：2.65 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
宽度：7.5 mmBase Number Matches：1

SN74ACT11478DW 数据手册

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SCAS131 − APRIL 1990 − REVISED APRIL 1993  
DW OR NT PACKAGE  
(TOP VIEW)  
• Inputs Are TTL-Voltage Compatible  
• Specifically Designed for Data  
Synchronization Applications  
1
24  
23  
22  
21  
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18  
17  
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15  
14  
13  
1Q  
2Q  
3Q  
4Q  
OE  
1D  
2D  
3D  
4D  
• Improved Metastable Characteristics  
2
Provide Greater System Reliability  
3
• 3-State Outputs Drive Bus Lines Directly  
4
5
GND  
GND  
GND  
GND  
5Q  
• Flow-Through Architecture to Optimize  
6
PCB Layout  
V
V
CC  
CC  
7
• Center-Pin V  
and GND Configurations to  
Minimize High-Speed Switching Noise  
CC  
8
5D  
6D  
9
• EPICt (Enhanced-Performance Implanted  
10  
11  
12  
6Q  
7Q  
8Q  
7D  
8D  
CLK  
CMOS) 1-mm Process  
• 500-mA Typical Latch-Up Immunity  
at 125°C  
• Package Options Include Plastic Small  
Outline Packages and Standard Plastic  
300-mil DIPs  
description  
The 74ACT11478 is an 8-bit dual-rank synchronizer circuit designed specifically for data synchronization  
applications where the normal setup and hold time specifications are frequently violated.  
Synchronization of two digital signals operating at different frequencies is a common system problem. This  
problem is typically solved by synchronizing one of the signals to the local clock through a flip-flop. This solution,  
however, causes the setup and hold time specifications associated with the flip-flop to be violated. When the  
setup or hold time specification is violated, the output response is uncertain.  
A flip-flop is metastable if its output hangs up in the region between V and V . The metastable condition lasts  
IL  
IH  
until the flip-flop recovers into one of its two stable states. With conventional flip-flops, this recovery time can  
be longer than the specified maximum propagation delay.  
The problem of metastability is typically solved by adding an additional layer of synchronization. This type of  
dual ranking is employed in the 74ACT11478. The probability of the second stage entering the metastable state  
is exponentially reduced by this dual-rank architecture. The 74ACT11478 provides a one-chip solution for  
system designers in asynchronous applications.  
The 74ACT11478 is characterized for operation from − 40°C to 85°C.  
FUNCTION TABLE  
(each flip-flop)  
INPUTS  
OUTPUT  
†
OE  
CLOCK  
D
Q
Z
L
H
L
L
L
X
↑
↑
H
X
L
H
X
H
Q
O
†
Data presented at the D input requires two  
clock cycles to appear at the Q output.  
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Copyright 1993, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
12345

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