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SN65MLVD204ADG4 PDF预览

SN65MLVD204ADG4

更新时间： 2024-11-06 04:31:19
品牌 Logo 应用领域
德州仪器 - TI 驱动器
页数 文件大小 规格书
26页 548K
描述
MULTIPOINT-LVDS LINE DRIVER AND RECEIVER

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SN65MLVD204ADG4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：SOP, SOP8,.25针数：8
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：6 weeks
风险等级：5.33差分输出：YES
驱动器位数：1高电平输入电流最大值：0.00001 A
输入特性：DIFFERENTIAL SCHMITT TRIGGER接口集成电路类型：LINE TRANSCEIVER
接口标准：EIA-899; TIA-899JESD-30 代码：R-PDSO-G8
JESD-609代码：e4长度：4.9 mm
湿度敏感等级：1功能数量：1
端子数量：8最高工作温度：85 °C
最低工作温度：-40 °C最小输出摆幅：0.48 V
输出特性：DIFFERENTIAL最大输出低电流：0.00001 A
输出极性：COMPLEMENTARY封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP8,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：260电源：3.3 V
认证状态：Not Qualified最大接收延迟：6 ns
接收器位数：1座面最大高度：1.75 mm
子类别：Line Driver or Receivers最大压摆率：24 mA
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V电源电压1-最大：3.6 V
电源电压1-分钟：3 V电源电压1-Nom：3.3 V
表面贴装：YES技术：BICMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
最大传输延迟：3.5 ns宽度：3.899 mm
Base Number Matches：1

SN65MLVD204ADG4 数据手册

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SN65MLVD200A, SN65MLVD202A  
SN65MLVD204A, SN65MLVD205A  
www.ti.com  
SLLS573–DECEMBER 2003  
MULTIPOINT-LVDS LINE DRIVER AND RECEIVER  
FEATURES  
DESCRIPTION  
•
Low-Voltage Differential 30-Ω to 55-Ω Line  
Drivers and Receivers for Signaling Rates  
Up to 100 Mbps, Clock Frequencies up to  
50 MHz  
The SN65MLVD200A, 202A, 204A, and 205A are  
multipoint-low-voltage differential (M-LVDS) line  
drivers and receivers, which are optimized to operate  
at signaling rates up to 100 Mbps. All parts comply  
with the multipoint low-voltage differential signaling  
(M-LVDS) standard TIA/EIA-899. These circuits are  
similar to their TIA/EIA-644 standard compliant LVDS  
counterparts, with added features to address  
multipoint applications. The driver output has been  
designed to support multipoint buses presenting  
loads as low as 30 Ω, and incorporates controlled  
transition times to allow for stubs off of the backbone  
transmission line.  
(1)  
•
•
Type-1 Receivers Incorporate 25 mV of  
Hysteresis (200A, 202A)  
Type-2 Receivers Provide an Offset(100 mV)  
Threshold to Detect Open-Circuit and Idle-Bus  
Conditions (204A, 205A)  
•
Meets or Exceeds the M-LVDS Standard  
TIA/EIA-899 for Multipoint Data Interchange  
•
•
Power Up/Down Glitch Free  
These devices have Type-1 and Type-2 receivers  
that detect the bus state with as little as 50 mV of  
Controlled Driver Output Voltage Transition  
Times for Improved Signal Quality  
differential input voltage over  
a common-mode  
•
–1 V to 3.4 V Common-Mode Voltage Range  
Allows Data Transfer With 2 V of Ground  
Noise  
voltage range of –1 V to 3.4 V. The Type-1 receivers  
exhibit 25 mV of differential input voltage hysteresis  
to prevent output oscillations with slowly changing  
signals or loss of input. Type-2 receivers include an  
offset threshold to provide a known output state  
under open-circuit, idle-bus, and other fault  
conditions.  
•
•
Bus Pins High Impedance When Disabled or  
VCC ≤ 1.5 V  
200-Mbps Devices Available (SN65MLVD201,  
203, 206, 207)  
The SN65MLVD200A, 202A, 204A, and 205A have  
enhancements over their predecessors. Improved  
features include better controlled slew rate on the  
driver output to help minimize reflections while  
improving overall signal integrity (SI) resulting in  
better jitter performance. Additionally, 8-kV ESD  
protection on the bus pins for more robustness. The  
same footprint definition was maintained making for  
•
•
Bus Pin ESD Protection Exceeds 8 kV  
Package in 8-Pin SOIC (200A, 204A) and  
14-Pin SOIC (202A, 205A)  
•
Improved Alternatives to the SN65MLVD200,  
202, 204, and 205  
APPLICATIONS  
•
an easy drop-in replacement for  
performance upgrade.  
a
system  
Low-Power High-Speed Short-Reach  
Alternative to TIA/EIA-485  
Backplane or Cabled Multipoint Data and  
Clock Transmission  
The devices are characterized for operation from  
–40°C to 85°C.  
•
•
•
•
Cellular Base Stations  
Central-Office Switches  
Network Switches and Routers  
(1) The signaling rate of a line, is the number of voltage  
transitions that are made per second expressed in the nits  
bps (bits per second).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2003–TBD, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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SN65MLVD204ADG4 替代型号

型号 品牌 替代类型 描述 数据表
SN65MLVD204ADR TI

完全替代

 MULTIPOINT-LVDS LINE DRIVER AND RECEIVER
SN65MLVD204AD TI

类似代替

 MULTIPOINT-LVDS LINE DRIVER AND RECEIVER
SN65MLVD204D TI

类似代替

 MULTIPOINT-LVDS LINE DRIVERS AND RECEIVERS

与SN65MLVD204ADG4相关器件

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SN65MLVD204ADR TI

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 		MULTIPOINT-LVDS LINE DRIVER AND RECEIVER
SN65MLVD204ADRG4 TI

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 		MULTIPOINT-LVDS LINE DRIVER AND RECEIVER
SN65MLVD204B TI

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 		高噪声抗扰度 100Mbps M-LVDS 收发器
SN65MLVD204B_V01 TI

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 		SN65MLVD204B Multipoint-LVDS Line Drivers and Receivers (Transceivers) With IEC ESD Protec
SN65MLVD204BD TI

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 		暂无描述
SN65MLVD204BDR TI

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 		高噪声抗扰度 100Mbps M-LVDS 收发器 | D | 8 | -40 to 85
SN65MLVD204BRUMR TI

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 		SN65MLVD204B Multipoint-LVDS Line Drivers and Receivers (Transceivers) With IEC ESD Protec
SN65MLVD204BRUMT TI

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 		SN65MLVD204B Multipoint-LVDS Line Drivers and Receivers (Transceivers) With IEC ESD Protec
SN65MLVD204D TI

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 		MULTIPOINT-LVDS LINE DRIVERS AND RECEIVERS
SN65MLVD204DRG4 TI

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 		Half-Duplex M-LVDS Transceiver 8-SOIC -40 to 85

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