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SN65HVD379 PDF预览

SN65HVD379

更新时间: 2024-11-17 05:18:11
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14页 515K
描述
3.3 V FULL-DUPLEX RS-485/RS-422 DRIVERS AND BALANCED RECEIVERS

SN65HVD379 数据手册

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SN65HVD379  
www.ti.com  
SLLS667AFEBRUARY 2006REVISED MAY 2006  
3.3 V FULL-DUPLEX RS-485/RS-422 DRIVERS AND BALANCED RECEIVERS  
FEATURES  
DESCRIPTION  
Designed for INTERBUS Applications  
The SN65HVD379 is a differential line driver and  
differential-input line receiver that operates with a  
3.3-V power supply. Each driver and receiver has  
separate input and output pins for full-duplex bus  
communication designs. They are designed for  
balanced transmission lines and interoperation with  
ANSI TIA/EIA-485A, TIA/EIA-422-B, ITU-T v.11, and  
ISO 8482:1993 standard-compliant devices.  
Balanced Receiver Thresholds  
1/2 Unit-Load (up to 64 nodes on the bus)  
Bus-Pin ESD Protection 15 kV HBM  
Bus-Fault Protection of –7V to 12V  
Thermal Shutdown Protection  
Power-Up/Down Glitch-free Bus Inputs and  
Outputs  
These differential bus drivers and receivers are  
monolithic, integrated circuits designed for full-duplex  
bi-directional data communication on multipoint  
bus-transmission lines at signaling rates(1) up to 25  
Mbps. The SN65HVD379 is fully enabled with no  
external enabling pins.  
High Input Impedance with Low VCC  
Monotonic Outputs During Power Cycling  
5V Tolerant Inputs  
APPLICATIONS  
The 1/2 unit load receiver has a higher receiver input  
resistance. This results in lower bus leakage currents  
over the common-mode voltage range, and reduces  
the total amount of current that an RS-485 driver is  
forced to source or sink when transmitting.  
Digital Motor Control  
Utility Meters  
Chassis-to-Chassis Interconnections  
Electronic Security Stations  
Industrial, Process, and Building Automation  
Point-of-Sale (POS) Terminals and Networks  
DTE/DCE Interfaces  
The balanced differential receiver input threshold  
makes the SN65HVD379 more compatible with  
fieldbus requirements that define an external failsafe  
structure.  
(1) The signaling rate of a line is the number of voltage  
transitions that are made per second expressed in the units  
bps (bits per second).  
BALANCED RECEIVER INPUT THRESHOLDS  
SN65HVD379  
D PACKAGE (TOP VIEW)  
Recevier Output High  
V
1
2
3
4
8
7
6
5
A
B
Z
Y
CC  
R
D
GND  
Receiver Output Low  
V
ID  
8
7
2
A
R
B
5
6
3
Y
Z
D
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2006, Texas Instruments Incorporated  

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