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SN54LVC138A PDF预览

SN54LVC138A

更新时间： 2024-11-03 23:03:07
品牌 Logo 应用领域
德州仪器 - TI 解码器解复用器
页数 文件大小 规格书
9页 146K
描述
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

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SN54LVC138A 数据手册

 浏览型号SN54LVC138A的Datasheet PDF文件第2页浏览型号SN54LVC138A的Datasheet PDF文件第3页浏览型号SN54LVC138A的Datasheet PDF文件第4页浏览型号SN54LVC138A的Datasheet PDF文件第5页浏览型号SN54LVC138A的Datasheet PDF文件第6页浏览型号SN54LVC138A的Datasheet PDF文件第7页 
SN54LVC138A, SN74LVC138A  
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS  
SCAS291I – MARCH 1993 – REVISED OCTOBER 1998  
SN54LVC138A . . . J OR W PACKAGE  
SN74LVC138A . . . D, DB, OR PW PACKAGE  
(TOP VIEW)  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
V
A
B
C
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
CC  
Y0  
Y1  
Y2  
Y3  
Y4  
Y5  
Y6  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
G2A  
G2B  
G1  
Y7  
GND  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
= 3.3 V, T = 25°C  
CC  
A
Typical V  
> 2 V at V  
(Output V  
Undershoot)  
OHV  
CC  
OH  
= 3.3 V, T = 25°C  
A
Inputs Accept Voltages to 5.5 V  
Package Options Include Plastic  
SN54LVC138A . . . FK PACKAGE  
(TOP VIEW)  
Small-Outline (D), Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
Packages, Ceramic Chip Carriers (FK) and  
Flat (W) Package, and DIPs (J)  
3
2 1 20 19  
18  
Y1  
Y2  
NC  
C
G2A  
NC  
4
5
6
7
8
description  
17  
16  
The SN54LVC138A 3-line to 8-line decoder/  
demultiplexer is designed for 2.7-V to 3.6-V V  
operation and the SN74LVC138A 3-line to 8-line  
decoder/demultiplexer is designed for 1.65-V to  
15 Y3  
14  
9 10 11 12 13  
G2B  
G1  
CC  
Y4  
3.6-V V  
operation.  
CC  
The ’LVC138A devices are designed for high-  
performance memory-decoding or data-routing  
applications requiring very short propagation  
NC – No internal connection  
delay times. In high-performance memory systems, these decoders minimize the effects of system decoding.  
When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and  
the enable time of the memory are usually less than the typical access time of the memory. This means that  
the effective system delay introduced by the decoders is negligible.  
The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two  
active-low enable inputs and one active-high enable input reduce the need for external gates or inverters when  
expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires  
only one inverter. An enable input can be used as a data input for demultiplexing applications.  
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators  
in a mixed 3.3-V/5-V system environment.  
The SN54LVC138A is characterized for operation over the full military temperature range of –55°C to 125°C.  
The SN74LVC138A is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1998, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

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