SN54LS107AJD

更新时间： 2024-11-23 13:00:11

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		触发器
页数	文件大小	规格书
4页	131K
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数据手册

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SN54LS107AJD 数据手册

SN54/74LS107A

DUAL JK NEGATIVE

EDGE-TRIGGERED FLIP-FLOP

The SN54/74LS107A is a Dual JK Flip-Flop with individual J, K, Direct

Clear and Clock Pulse inputs. Output changes are initiated by the

HIGH-to-LOW transition of the clock. A LOW signal on CD input overrides the

other inputs and makes the Q output LOW.

The SN54/74LS107A is the same as the SN54/74LS73A but has corner

power pins.

DUAL JK NEGATIVE

EDGE-TRIGGERED FLIP-FLOP

LOW POWER SCHOTTKY

CONNECTION DIAGRAM DIP (TOP VIEW)

J SUFFIX

CERAMIC

CASE 632-08

NOTE:

The Flatpak version has the

same pinouts (Connection

Diagram) as the Dual In-Line

Package.

N SUFFIX

PLASTIC

CASE 646-06

D SUFFIX

SOIC

CASE 751A-02

LOGIC SYMBOL

ORDERING INFORMATION

SN54LSXXXJ Ceramic

SN74LSXXXN Plastic

SN74LSXXXD SOIC

GUARANTEED OPERATING RANGES

Symbol

Parameter

Min

Typ

Max

Unit

Supply Voltage

4.5

4.75

5.0

5.5

5.25

Operating Ambient Temperature Range

–55

125

°C

Output Current — High

Output Current — Low

54, 74

–0.4

4.0

8.0

FAST AND LS TTL DATA

5-177

12 3 4

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与SN54LS107AJD相关器件

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SN54LS109A-SP	TI	获取价格	DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR
SN54LS109AW	TI	获取价格	DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR