Datasheet > SN54LS109J

SN54LS109J

更新时间： 2024-09-15 23:03:03

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		触发器
页数	文件大小	规格书
4页	150K
描述
DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP

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数据手册

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SN54LS109J 数据手册

SN54/74LS109A

DUAL JK POSITIVE

EDGE-TRIGGERED FLIP-FLOP

The SN54/74LS109A consists of two high speed completely independent

transition clocked JK flip-flops. The clocking operation is independent of rise

and fall times of the clock waveform. The JK design allows operation as a D

flip-flop by simply connecting the J and K pins together.

DUAL JK POSITIVE

EDGE-TRIGGERED FLIP-FLOP

LOW POWER SCHOTTKY

LOGIC DIAGRAM

J SUFFIX

CERAMIC

CASE 620-09

N SUFFIX

PLASTIC

CASE 648-08

D SUFFIX

SOIC

CASE 751B-03

MODE SELECT — TRUTH TABLE

INPUTS

OUTPUTS

OPERATING MODE

ORDERING INFORMATION

SN54LSXXXJ Ceramic

SN74LSXXXN Plastic

SN74LSXXXD SOIC

Set

Reset (Clear)

*Undetermined

Load “1” (Set)

Hold

Toggle

Load “0” (Reset)

LOGIC SYMBOL

* BothoutputswillbeHIGHwhilebothS andC areLOW,buttheoutputstates

are unpredictable if S and C go HIGH simultaneously.

H, h = HIGH Voltage Level

L, I = LOW Voltage Level

X = Don’t Care

l, h (q) = Lower case letters indicate the state of the referenced input (or output)

l, h (q) = one set-up time prior to the LOW to HIGH clock transition.

FAST AND LS TTL DATA

5-181

12 3 4

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与SN54LS109J相关器件

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SN54LS10J	TI	获取价格	TRIPLE 3-INPUT POSITIVE-NAND GATES
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SN54LS10W	TI	获取价格	TRIPLE 3-INPUT POSITIVE-NAND GATES
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SN54LS10W-00	TI	获取价格	IC LS SERIES, TRIPLE 3-INPUT NAND GATE, CDFP14, Gate