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SN54HC595J-00 PDF预览

SN54HC595J-00

更新时间： 2024-11-23 15:51:59
品牌 Logo 应用领域
德州仪器 - TI 输出元件逻辑集成电路触发器
页数 文件大小 规格书
27页 1213K
描述
HC/UH SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CDIP16

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SN54HC595J-00 技术参数

生命周期：Obsolete包装说明：DIP,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.59其他特性：PARALLEL OUTPUT IS REGISTERED; UNREGISTERED SERIAL SHIFT RIGHT OUTPUT
计数方向：RIGHT系列：HC/UH
JESD-30 代码：R-GDIP-T16长度：19.56 mm
负载电容（CL）：50 pF逻辑集成电路类型：SERIAL IN PARALLEL OUT
位数：8功能数量：1
端子数量：16最高工作温度：125 °C
最低工作温度：-55 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：CERAMIC, GLASS-SEALED
封装代码：DIP封装形状：RECTANGULAR
封装形式：IN-LINE传播延迟（tpd）：48 ns
认证状态：Not Qualified座面最大高度：5.08 mm
最大供电电压 (Vsup)：6 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：CMOS温度等级：MILITARY
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL触发器类型：POSITIVE EDGE
宽度：7.62 mm最小 fmax：21 MHz
Base Number Matches：1

SN54HC595J-00 数据手册

 浏览型号SN54HC595J-00的Datasheet PDF文件第2页浏览型号SN54HC595J-00的Datasheet PDF文件第3页浏览型号SN54HC595J-00的Datasheet PDF文件第4页浏览型号SN54HC595J-00的Datasheet PDF文件第5页浏览型号SN54HC595J-00的Datasheet PDF文件第6页浏览型号SN54HC595J-00的Datasheet PDF文件第7页 
SN54HC595  
SN74HC595  
www.ti.com  
SCLS041H –DECEMBER 1982–REVISED NOVEMBER 2009  
8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS  
Check for Samples: SN54HC595 SN74HC595  
1
FEATURES  
SN54HC595...J OR W PACKAGE  
SN74HC595...D, DB, DW, N, NS, OR PW PACKAGE  
(TOP VIEW)  
•
•
•
8-Bit Serial-In, Parallel-Out Shift  
Wide Operating Voltage Range of 2 V to 6 V  
High-Current 3-State Outputs Can Drive Up To  
15 LSTTL Loads  
Q
Q
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
B
Q
C
D
A
•
•
•
•
•
Low Power Consumption: 80-μA (Max) ICC  
tpd = 13 ns (Typ)  
Q
SER  
OE  
Q
E
Q
Q
12 RCLK  
F
±6-mA Output Drive at 5 V  
11  
10  
9
SRCLK  
SRCLR  
G
Low Input Current: 1 μA (Max)  
Shift Register Has Direct Clear  
Q
H
GND  
Q ′  
H
DESCRIPTION  
SN54HC595...FK PACKAGE  
(TOP VIEW)  
The 'HC595 devices contain an 8-bit serial-in,  
parallel-out shift register that feeds an 8-bit D-type  
storage register. The storage register has parallel  
3-state outputs. Separate clocks are provided for both  
the shift and storage register. The shift register has a  
direct overriding clear (SRCLR) input, serial (SER)  
input, and serial outputs for cascading. When the  
output-enable (OE) input is high, the outputs are in  
the high-impedance state.  
3
2
1
2 0 1 9  
18  
SER  
OE  
Q
4
5
6
7
8
D
Q
17  
16  
E
NC  
NC  
15 RCLK  
Q
F
14  
9 10 11 12 1 3  
Both the shift register clock (SRCLK) and storage  
register clock (RCLK) are positive-edge triggered. If  
both clocks are connected together, the shift register  
always is one clock pulse ahead of the storage  
register.  
SRCLK  
Q
G
NC – No internal connection  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1982–2009, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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