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ꢊ ꢅꢋꢌꢍ ꢎꢏꢀ ꢋ ꢐꢌꢁꢀꢅ ꢑ ꢒꢓ ꢑ ꢐ
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SCLS303D − JANUARY 1996 − REVISED AUGUST 2003
D
D
D
Wide Operating Voltage Range of 2 V to 6 V
D
D
D
D
Typical t = 8 ns
pd
6-mA Output Drive at 5 V
High-Current 3-State Outputs Can Drive Up
To 15 LSTTL Loads
Low Input Current of 1 µA Max
Inverting Logic
Low Power Consumption, 80-µA Max I
CC
SN54HC640 . . . FK PACKAGE
(TOP VIEW)
SN54HC640 . . . J OR W PACKAGE
SN74HC640 . . . DW, N, NS, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
DIR
A1
A2
A3
A4
A5
A6
A7
A8
V
CC
3
2
1
20 19
18
OE
B1
B2
B3
B4
B5
B6
B7
B8
B1
B2
B3
B4
B5
A3
A4
A5
A6
A7
4
5
6
7
8
17
16
15
14
9 10 11 12 13
GND
description/ordering information
These octal bus transceivers are designed for asynchronous two-way communication between data buses.
These devices transmit data from the A bus to the B bus or from the B bus to the A bus, depending upon the
level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the
buses are effectively isolated.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP − N
Tube of 20
Tube of 25
Reel of 2000
Reel of 2000
Tube of 70
Reel of 2000
Reel of 250
Tube of 20
Tube of 85
Tube of 55
SN74HC640N
SN74HC640N
SN74HC640DW
SN74HC640DWR
SN74HC640NSR
SN74HC640PW
SN74HC640PWR
SN74HC640PWT
SNJ54HC640J
SOIC − DW
SOP − NS
HC640
HC640
−40°C to 85°C
TSSOP − PW
HC640
CDIP − J
CFP − W
LCCC − FK
SNJ54HC640J
SNJ54HC640W
SNJ54HC640FK
−55°C to 125°C
SNJ54HC640W
SNJ54HC640FK
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2003, Texas Instruments Incorporated
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