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SN54HC646WR PDF预览

SN54HC646WR

更新时间： 2024-11-09 20:07:27
品牌 Logo 应用领域
德州仪器 - TI 输出元件逻辑集成电路
页数 文件大小 规格书
10页 175K
描述
HC/UH SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, CDFP24, CERAMIC, FP-24

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SN54HC646WR 技术参数

生命周期：Obsolete零件包装代码：DFP
包装说明：DFP,针数：24
Reach Compliance Code：unknown风险等级：5.74
其他特性：WITH DIRECTION CONTROL系列：HC/UH
JESD-30 代码：R-GDFP-F24长度：14.36 mm
负载电容（CL）：150 pF逻辑集成电路类型：REGISTERED BUS TRANSCEIVER
位数：8功能数量：1
端口数量：2端子数量：24
最高工作温度：125 °C最低工作温度：-55 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DFP
封装形状：RECTANGULAR封装形式：FLATPACK
传播延迟（tpd）：400 ns认证状态：Not Qualified
座面最大高度：2.29 mm最大供电电压 (Vsup)：6 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子形式：FLAT
端子节距：1.27 mm端子位置：DUAL
宽度：9.09 mmBase Number Matches：1

SN54HC646WR 数据手册

 浏览型号SN54HC646WR的Datasheet PDF文件第2页浏览型号SN54HC646WR的Datasheet PDF文件第3页浏览型号SN54HC646WR的Datasheet PDF文件第4页浏览型号SN54HC646WR的Datasheet PDF文件第5页浏览型号SN54HC646WR的Datasheet PDF文件第6页浏览型号SN54HC646WR的Datasheet PDF文件第7页 
SN54HC646, SN74HC646  
OCTAL BUS TRANSCEIVERS AND REGISTERS  
WITH 3-STATE OUTPUTS  
SCLS150B – DECEMBER 1982 – REVISED MAY 1997  
SN54HC646 . . . JT OR W PACKAGE  
SN74HC646 . . . DW OR NT PACKAGE  
(TOP VIEW)  
Independent Registers for A and B Buses  
Multiplexed Real-Time and Stored Data  
True Data Paths  
CLKAB  
SAB  
DIR  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
GND  
V
CC  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
High-Current 3-State Outputs Can Drive up  
to 15 LSTTL Loads  
CLKBA  
SBA  
OE  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
2
3
Package Options Include Plastic  
Small-Outline (DW) and Ceramic Flat (W)  
Packages, Ceramic Chip Carriers (FK), and  
Standard Plastic (NT) and Ceramic (JT)  
300-mil DIPs  
4
5
6
7
8
9
description  
10  
11  
12  
The ’HC646 consist of bus-transceiver circuits  
with 3-state outputs, D-type flip-flops, and control  
circuitry arranged for multiplexed transmission of  
data directly from the input bus or from the internal  
registers. DataontheAorBbusisclockedintothe  
registers on the low-to-high transition of the  
appropriate clock (CLKAB or CLKBA) input.  
Figure 1 illustrates the four fundamental bus-  
management functions that can be performed  
with the ’HC646.  
B8  
SN54HC646 . . . FK PACKAGE  
(TOP VIEW)  
4
3
2
1
28 27 26  
25  
A1  
A2  
A3  
NC  
A4  
OE  
B1  
B2  
NC  
B3  
B4  
B5  
5
6
7
8
9
Output-enable (OE) and direction-control (DIR)  
inputs control the transceiver functions. In the  
transceiver mode, data present at the  
high-impedance port may be stored in either or  
both registers.  
24  
23  
22  
21  
20  
19  
A5 10  
11  
The select-control (SAB and SBA) inputs can  
multiplex stored and real-time (transparent mode)  
data. DIR determines which bus receives data  
when OE is active (low). In the isolation mode (OE  
high), A data may be stored in one register and/or  
B data may be stored in the other register.  
A6  
12 13 14 15 16 17 18  
NC – No internal connection  
When an output function is disabled, the input function is still enabled and can be used to store and transmit  
data. Only one of the two buses, A or B, may be driven at a time.  
The SN54HC646 is characterized for operation over the full military temperature range of –55°C to 125°C. The  
SN74HC646 is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1997, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...10

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