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SN54HC4060J-00 PDF预览

SN54HC4060J-00

更新时间: 2024-11-26 15:51:59
品牌 Logo 应用领域
德州仪器 - TI 输入元件输出元件逻辑集成电路触发器
页数 文件大小 规格书
20页 1050K
描述
HC/UH SERIES, ASYN NEGATIVE EDGE TRIGGERED 14-BIT UP BINARY COUNTER, CDIP16

SN54HC4060J-00 技术参数

生命周期:ObsoleteReach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.72
Is Samacsys:N其他特性:OUTPUTS FROM 10 STAGES AVAILABLE; BUILT-IN OSCILLATOR; OSCILLATOR DISABLED BY CLEAR INPUT
计数方向:UP系列:HC/UH
JESD-30 代码:R-GDIP-T16长度:19.56 mm
负载电容(CL):50 pF负载/预设输入:YES
逻辑集成电路类型:BINARY COUNTER工作模式:ASYNCHRONOUS
位数:14功能数量:1
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE传播延迟(tpd):735 ns
认证状态:Not Qualified座面最大高度:5.08 mm
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL触发器类型:NEGATIVE EDGE
宽度:7.62 mm最小 fmax:19 MHz
Base Number Matches:1

SN54HC4060J-00 数据手册

 浏览型号SN54HC4060J-00的Datasheet PDF文件第2页浏览型号SN54HC4060J-00的Datasheet PDF文件第3页浏览型号SN54HC4060J-00的Datasheet PDF文件第4页浏览型号SN54HC4060J-00的Datasheet PDF文件第5页浏览型号SN54HC4060J-00的Datasheet PDF文件第6页浏览型号SN54HC4060J-00的Datasheet PDF文件第7页 
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ꢊ ꢃ ꢋꢀꢌꢍꢎ ꢏ ꢍꢀ ꢐꢁ ꢅꢄꢑꢒ ꢁꢒ ꢓꢀ ꢔꢕ ꢁꢍꢑꢐ ꢅꢒ ꢓꢁꢌ ꢏꢑ ꢀ ꢍꢁꢖ ꢒ ꢀꢅꢕ ꢗꢗ ꢍꢌꢒ ꢑꢀ  
SCLS161D − DECEMBER 1982 − REVISED SEPTEMBER 2003  
D
D
D
D
Wide Operating Voltage Range of 2 V to 6 V  
Outputs Can Drive Up To 10 LSTTL Loads  
D
D
D
4-mA Output Drive at 5 V  
Low Input Current of 1 µA Max  
Allow Design of Either RC- or  
Crystal-Oscillator Circuits  
Low Power Consumption, 80-µA Max I  
CC  
Typical t = 14 ns  
pd  
SN54HC4060 . . . J OR W PACKAGE  
SN74HC4060 . . . D, DB, N, NS, OR PW PACKAGE  
(TOP VIEW)  
SN54HC4060 . . . FK PACKAGE  
(TOP VIEW)  
Q
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
L
3
2
1
20 19  
18  
Q
Q
Q
Q
M
J
H
I
Q
Q
Q
4
5
6
7
8
H
I
N
Q
N
Q
17  
16  
F
Q
F
E
NC  
NC  
Q
12 CLR  
15 CLR  
14  
9 10 11 12 13  
Q
E
11  
10  
9
Q
CLKI  
G
CLKI  
Q
G
Q
CLKO  
CLKO  
D
GND  
NC − No internal connection  
description/ordering information  
The ’HC4060 devices consist of an oscillator section and 14 ripple-carry binary counter stages. The oscillator  
configuration allows design of either RC- or crystal-oscillator circuits. A high-to-low transition on the clock (CLKI)  
input increments the counter. A high level at the clear (CLR) input disables the oscillator (CLKO goes high and  
CLKO goes low) and resets the counter to zero (all Q outputs low).  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP − N  
SOIC − D  
Tube of 25  
Tube of 40  
Reel of 2500  
Reel of 250  
Reel of 2000  
Reel of 2000  
Tube of 90  
Reel of 2000  
Reel of 250  
Tube of 25  
Tube of 150  
Tube of 55  
SN74HC4060N  
SN74HC4060N  
SN74HC4060D  
SN74HC4060DR  
SN74HC4060DT  
SN74HC4060NSR  
SN74HC4060DBR  
SN74HC4060PW  
SN74HC4060PWR  
SN74HC4060PWT  
SNJ54HC4060J  
SNJ54HC4060W  
SNJ54HC4060FK  
HC4060  
SOP − NS  
HC4060  
HC4060  
−40°C to 85°C  
SSOP − DB  
TSSOP − PW  
HC4060  
CDIP − J  
CFP − W  
LCCC − FK  
SNJ54HC4060J  
SNJ54HC4060W  
SNJ54HC4060FK  
−55°C to 125°C  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
ꢒ ꢚ ꢥ ꢝ ꢜꢨ ꢣꢢ ꢠꢡ ꢢꢜ ꢞꢥ ꢧꢙ ꢟꢚ ꢠ ꢠꢜ ꢯꢕ ꢗꢋ ꢘꢑ ꢰ ꢋꢱꢲꢂ ꢱꢂꢈ ꢟꢧꢧ ꢥꢟ ꢝ ꢟ ꢞꢤ ꢠꢤꢝ ꢡ ꢟ ꢝ ꢤ ꢠꢤ ꢡꢠꢤ ꢨ  
ꢠ ꢤ ꢡ ꢠꢙ ꢚꢮ ꢜꢛ ꢟ ꢧꢧ ꢥꢟ ꢝ ꢟ ꢞ ꢤ ꢠ ꢤ ꢝ ꢡ ꢩ  
ꢣ ꢚꢧ ꢤꢡꢡ ꢜ ꢠꢪꢤ ꢝ ꢬꢙ ꢡꢤ ꢚ ꢜꢠꢤ ꢨꢩ ꢒ ꢚ ꢟꢧ ꢧ ꢜ ꢠꢪꢤ ꢝ ꢥꢝ ꢜ ꢨꢣꢢ ꢠꢡ ꢈ ꢥꢝ ꢜ ꢨꢣꢢ ꢠꢙꢜ ꢚ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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