ꢀꢁꢂ ꢃ ꢄꢅ ꢃ ꢆꢇ ꢀꢁ ꢈꢃ ꢄꢅ ꢃꢆ
ꢃ ꢉꢊ ꢋꢁꢌ ꢍ ꢎ ꢏ ꢐ ꢉꢊ ꢋꢁꢌ ꢑꢌꢅ ꢎꢑ ꢌꢒ ꢀ ꢓ ꢏ ꢔꢕ ꢏꢐ ꢖ
SCLS091D − DECEMBER 1982 − REVISED SEPTEMBER 2003
D
D
D
D
D
Wide Operating Voltage Range of 2 V to 6 V
Outputs Can Drive Up To 10 LSTTL Loads
D
D
D
D
Low Input Current of 1 µA Max
Full Decoding of Input Logic
Low Power Consumption, 80-µA Max I
All Outputs Are High for Invalid BCD
Conditions
CC
Typical t = 14 ns
pd
4-mA Output Drive at 5 V
Also for Applications as 3-Line to 8-Line
Decoders
SN54HC42 . . . J OR W PACKAGE
SN74HC42 . . . D, N, OR NS PACKAGE
(TOP VIEW)
SN54HC42 . . . FK PACKAGE
(TOP VIEW)
0
V
A
B
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CC
3
2
1
20 19
18
1
B
2
3
4
5
6
7
8
2
C
17
16
15
14
3
C
D
9
NC
D
NC
4
4
5
9
5
9 10 11 12 13
6
8
GND
7
NC − No internal connection
description/ordering information
These decimal decoders consist of eight inverters and ten 4-input NAND gates. The inverters are connected
in pairs to make BCD input data available for decoding by the NAND gates. Full decoding of valid input logic
ensures that all inputs remain off for all invalid input conditions.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP − N
SOIC − D
Tube of 25
Tube of 40
Reel of 2500
Reel of 250
Reel of 2000
Tube of 25
Tube of 150
Tube of 55
SN74HC42N
SN74HC42N
SN74HC42D
SN74HC42DR
SN74HC42DT
SN74HC42NSR
SNJ54HC42J
SNJ54HC42W
SNJ54HC42FK
−40°C to 85°C
HC42
SOP − NS
CDIP − J
HC42
SNJ54HC42J
SNJ54HC42W
SNJ54HC42FK
−55°C to 125°C
CFP − W
LCCC − FK
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2003, Texas Instruments Incorporated
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