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SN54HC377FH PDF预览

SN54HC377FH

更新时间: 2024-11-02 12:58:31
品牌 Logo 应用领域
德州仪器 - TI 触发器时钟
页数 文件大小 规格书
13页 425K
描述
IC,FLIP-FLOP,OCTAL,D TYPE,HC-CMOS,LLCC,20PIN,CERAMIC

SN54HC377FH 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:QCCN, LCC20,.35SQReach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.92
JESD-30 代码:S-XQCC-N20逻辑集成电路类型:D FLIP-FLOP
功能数量:8端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC封装代码:QCCN
封装等效代码:LCC20,.35SQ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):NOT SPECIFIED
电源:2/6 V认证状态:Not Qualified
子类别:FF/Latches表面贴装:YES
技术:CMOS温度等级:MILITARY
端子形式:NO LEAD端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGEBase Number Matches:1

SN54HC377FH 数据手册

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ꢉ ꢅꢊꢋꢌ ꢍꢎꢊ ꢏꢐ ꢑ ꢒ ꢌꢓ ꢐ ꢎꢒ ꢌꢉ ꢐ  
SCLS307B– JANUARY 1996 – REVISED JANUARY 2003  
SN54HC377 . . . J OR W PACKAGE  
SN74HC377 . . . DW, N, OR NS PACKAGE  
(TOP VIEW)  
D
D
D
D
D
D
D
D
Wide Operating Voltage Range of 2 V to 6 V  
Outputs Can Drive Up To 10 LSTTL Loads  
Low Power Consumption, 80-µA Max I  
CC  
CLKEN  
1Q  
V
CC  
8Q  
8D  
1
2
3
4
5
6
7
8
9
20  
19  
18  
Typical t = 12 ns  
pd  
±4-mA Output Drive at 5 V  
1D  
Low Input Current of 1 µA Max  
Eight Flip-Flops With Single-Rail Outputs  
2D  
17 7D  
16 7Q  
15 6Q  
2Q  
3Q  
Clock Enable Latched to Avoid False  
Clocking  
3D  
14  
6D  
4D  
13 5D  
12 5Q  
11 CLK  
D
Applications Include:  
– Buffer/Storage Registers  
– Shift Registers  
4Q  
GND 10  
– Pattern Generators  
SN54HC377 . . . FK PACKAGE  
(TOP VIEW)  
description/ordering information  
These devices are positive-edge-triggered octal  
D-type flip-flops with an enable input. The ’HC377  
devices are similar to the ’HC273 devices, but  
feature a latched clock-enable (CLKEN) input  
instead of a common clear.  
3
2
1
20 19  
18  
8D  
7D  
7Q  
2D  
2Q  
3Q  
3D  
4D  
4
5
6
7
8
17  
16  
Information at the data (D) inputs meeting the  
setup time requirements is transferred to the  
Q outputs on the positive-going edge of the clock  
(CLK) pulse, if CLKEN is low. Clock triggering  
occurs at a particular voltage level and is not  
directly related to the transition time of the  
positive-going pulse. When CLK is at either the  
high or low level, the D input has no effect at the  
output. These devices are designed to prevent  
false clocking by transitions at CLKEN.  
15 6Q  
14  
6D  
9 10 11 12 13  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP – N  
Tube  
SN74HC377N  
SN74HC377N  
Tube  
SN74HC377DW  
SN74HC377DWR  
SN74HC377NSR  
SNJ54HC377J  
SNJ54HC377W  
SNJ54HC377FK  
–40°C to 85°C  
SOIC – DW  
HC377  
Tape and reel  
Tape and reel  
Tube  
SOP – NS  
CDIP – J  
HC377  
SNJ54HC377J  
SNJ54HC377W  
SNJ54HC377FK  
CFP – W  
LCCC – FK  
Tube  
–55°C to 125°C  
Tube  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
ꢉ ꢚ ꢥ ꢝ ꢜꢨ ꢣꢢ ꢠꢡ ꢢꢜ ꢞꢥ ꢧꢙ ꢟꢚ ꢠ ꢠꢜ ꢯꢓ ꢌꢎ ꢐꢗ ꢒ ꢎꢆꢰꢂ ꢆꢂꢈ ꢟꢧꢧ ꢥꢟ ꢝ ꢟ ꢞꢤ ꢠꢤꢝ ꢡ ꢟ ꢝ ꢤ ꢠꢤ ꢡꢠꢤ ꢨ  
ꢠ ꢤ ꢡ ꢠꢙ ꢚꢮ ꢜꢛ ꢟ ꢧꢧ ꢥꢟ ꢝ ꢟ ꢞ ꢤ ꢠ ꢤ ꢝ ꢡ ꢩ  
ꢣ ꢚꢧ ꢤꢡꢡ ꢜ ꢠꢪꢤ ꢝ ꢬꢙ ꢡꢤ ꢚ ꢜꢠꢤ ꢨꢩ ꢉ ꢚ ꢟꢧ ꢧ ꢜ ꢠꢪꢤ ꢝ ꢥꢝ ꢜ ꢨꢣꢢ ꢠꢡ ꢈ ꢥꢝ ꢜ ꢨꢣꢢ ꢠꢙꢜ ꢚ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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