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SN54HC374J-00 PDF预览

SN54HC374J-00

更新时间: 2024-11-23 15:51:59
品牌 Logo 应用领域
德州仪器 - TI 驱动输出元件逻辑集成电路
页数 文件大小 规格书
23页 1183K
描述
HC/UH SERIES, 8-BIT DRIVER, TRUE OUTPUT, CDIP20

SN54HC374J-00 技术参数

生命周期:Obsolete包装说明:DIP,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.08系列:HC/UH
JESD-30 代码:R-GDIP-T20长度:24.195 mm
负载电容(CL):150 pF逻辑集成电路类型:BUS DRIVER
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
传播延迟(tpd):69 ns认证状态:Not Qualified
座面最大高度:5.08 mm最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
宽度:7.62 mmBase Number Matches:1

SN54HC374J-00 数据手册

 浏览型号SN54HC374J-00的Datasheet PDF文件第2页浏览型号SN54HC374J-00的Datasheet PDF文件第3页浏览型号SN54HC374J-00的Datasheet PDF文件第4页浏览型号SN54HC374J-00的Datasheet PDF文件第5页浏览型号SN54HC374J-00的Datasheet PDF文件第6页浏览型号SN54HC374J-00的Datasheet PDF文件第7页 
ꢉ ꢅꢊꢋꢌ ꢍꢎ ꢏꢍ ꢐꢊꢑ ꢒꢏ ꢏꢍ ꢑꢍꢎ ꢎꢐꢊ ꢓꢔ ꢍ ꢕ ꢌꢒ ꢔ ꢐꢕ ꢌꢉ ꢔ  
SCLS141E − DECEMBER 1982 − REVISED AUGUST 2003  
D
D
Wide Operating Voltage Range of 2 V to 6 V  
D
D
D
D
Low Power Consumption, 80-µA Max I  
Typical t = 14 ns  
pd  
6-mA Output Drive at 5 V  
CC  
High-Current 3-State True Outputs Can  
Drive Up To 15 LSTTL Loads  
D
Eight D-Type Flip-Flops in a Single Package  
Full Parallel Access for Loading  
Low Input Current of 1 µA Max  
D
SN54HC374 . . . FK PACKAGE  
(TOP VIEW)  
SN54HC374 . . . J OR W PACKAGE  
SN74HC374 . . . DB, DW, N, NS, OR PW PACKAGE  
(TOP VIEW)  
OE  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
V
CC  
8Q  
8D  
1
2
3
4
5
6
7
8
9
20  
19  
18  
3
2
1
20 19  
18  
8D  
7D  
7Q  
2D  
2Q  
3Q  
3D  
4D  
4
5
6
7
8
17  
16  
17 7D  
16 7Q  
15 6Q  
14 6D  
13 5D  
12 5Q  
11 CLK  
15 6Q  
14  
9 10 11 12 13  
6D  
GND 10  
description/ordering information  
These 8-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively  
low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional  
bus drivers, and working registers.  
The eight flip-flops of the ’HC374 devices are edge-triggered D-type flip-flops. On the positive transition of the  
clock (CLK) input, the Q outputs are set to the logic levels that were set up at the data (D) inputs.  
An output-enable (OE) input places the eight outputs in either a normal logic state (high or low logic levels) or  
the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines  
significantly. The high-impedance state and increased drive provide the capability to drive bus lines without  
interface or pullup components.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP − N  
Tube of 20  
Tube of 25  
Reel of 2000  
Reel of 2000  
Reel of 2000  
Tube of 2000  
Reel of 250  
Tube of 20  
Tube of 85  
Tube of 55  
SN74HC374N  
SN74HC374N  
SN74HC374DW  
SN74HC374DWR  
SN74HC374NSR  
SN74HC374DBR  
SN74HC374PWR  
SN74HC374PWT  
SNJ54HC374J  
SOIC − DW  
HC374  
SOP − NS  
HC374  
HC374  
−40°C to 85°C  
−55°C to 125°C  
SSOP − DB  
TSSOP − PW  
HC374  
CDIP − J  
CFP − W  
LCCC − FK  
SNJ54HC374J  
SNJ54HC374W  
SNJ54HC374FK  
SNJ54HC374W  
SNJ54HC374FK  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
ꢉ ꢙ ꢤ ꢜ ꢛꢧ ꢢꢡ ꢟꢠ ꢡꢛ ꢝꢤ ꢦꢘ ꢞꢙ ꢟ ꢟꢛ ꢮꢒ ꢌꢐ ꢔꢑ ꢕ ꢐꢆꢯꢂ ꢆꢂꢈ ꢞꢦꢦ ꢤꢞ ꢜ ꢞ ꢝꢣ ꢟꢣꢜ ꢠ ꢞ ꢜ ꢣ ꢟꢣ ꢠꢟꢣ ꢧ  
ꢟ ꢣ ꢠ ꢟꢘ ꢙꢭ ꢛꢚ ꢞ ꢦꢦ ꢤꢞ ꢜ ꢞ ꢝ ꢣ ꢟ ꢣ ꢜ ꢠ ꢨ  
ꢢ ꢙꢦ ꢣꢠꢠ ꢛ ꢟꢩꢣ ꢜ ꢫꢘ ꢠꢣ ꢙ ꢛꢟꢣ ꢧꢨ ꢉ ꢙ ꢞꢦ ꢦ ꢛ ꢟꢩꢣ ꢜ ꢤꢜ ꢛ ꢧꢢꢡ ꢟꢠ ꢈ ꢤꢜ ꢛ ꢧꢢꢡ ꢟꢘꢛ ꢙ  
ꢝꢣ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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