ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢃ
ꢈ
ꢀ
ꢁ
ꢇ
ꢉ ꢅꢊꢋꢌ ꢍꢎ ꢏꢍ ꢐꢊꢑ ꢒꢏ ꢏꢍ ꢑꢍꢎ ꢎꢐꢊ ꢓꢔ ꢍ ꢕ ꢌꢒ ꢔ ꢐꢕ ꢌꢉ ꢔ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢃ
ꢀ
ꢀ
ꢖ
ꢒ
ꢊ
ꢄ
ꢆ
ꢐ
ꢀ
ꢊ
ꢋ
ꢊ
ꢍ
ꢉ
ꢗ
ꢊ
ꢔ
ꢗ
ꢊ
SCLS141E − DECEMBER 1982 − REVISED AUGUST 2003
D
D
Wide Operating Voltage Range of 2 V to 6 V
D
D
D
D
Low Power Consumption, 80-µA Max I
Typical t = 14 ns
pd
6-mA Output Drive at 5 V
CC
High-Current 3-State True Outputs Can
Drive Up To 15 LSTTL Loads
D
Eight D-Type Flip-Flops in a Single Package
Full Parallel Access for Loading
Low Input Current of 1 µA Max
D
SN54HC374 . . . FK PACKAGE
(TOP VIEW)
SN54HC374 . . . J OR W PACKAGE
SN74HC374 . . . DB, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
V
CC
8Q
8D
1
2
3
4
5
6
7
8
9
20
19
18
3
2
1
20 19
18
8D
7D
7Q
2D
2Q
3Q
3D
4D
4
5
6
7
8
17
16
17 7D
16 7Q
15 6Q
14 6D
13 5D
12 5Q
11 CLK
15 6Q
14
9 10 11 12 13
6D
GND 10
description/ordering information
These 8-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively
low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers.
The eight flip-flops of the ’HC374 devices are edge-triggered D-type flip-flops. On the positive transition of the
clock (CLK) input, the Q outputs are set to the logic levels that were set up at the data (D) inputs.
An output-enable (OE) input places the eight outputs in either a normal logic state (high or low logic levels) or
the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide the capability to drive bus lines without
interface or pullup components.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP − N
Tube of 20
Tube of 25
Reel of 2000
Reel of 2000
Reel of 2000
Tube of 2000
Reel of 250
Tube of 20
Tube of 85
Tube of 55
SN74HC374N
SN74HC374N
SN74HC374DW
SN74HC374DWR
SN74HC374NSR
SN74HC374DBR
SN74HC374PWR
SN74HC374PWT
SNJ54HC374J
SOIC − DW
HC374
SOP − NS
HC374
HC374
−40°C to 85°C
−55°C to 125°C
SSOP − DB
TSSOP − PW
HC374
CDIP − J
CFP − W
LCCC − FK
SNJ54HC374J
SNJ54HC374W
SNJ54HC374FK
SNJ54HC374W
SNJ54HC374FK
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
ꢔ
ꢔ
ꢑ
ꢉ
ꢧ
ꢎ
ꢢ
ꢞ
ꢗ
ꢅ
ꢠ
ꢊ
ꢡ
ꢫ
ꢒ
ꢛ
ꢉ
ꢙ
ꢜ
ꢁ
ꢚ
ꢎ
ꢋ
ꢊ
ꢋ
ꢘ
ꢙ
ꢣ
ꢢ
ꢚ
ꢛ
ꢡ
ꢡ
ꢜ
ꢝ
ꢞ
ꢞ
ꢙ
ꢟ
ꢟ
ꢘ
ꢘ
ꢤ
ꢛ
ꢛ
ꢜ
ꢙ
ꢙ
ꢛ
ꢘ
ꢠ
ꢠ
ꢤ
ꢠ
ꢡ
ꢢ
ꢜ
ꢜ
ꢣ
ꢣ
ꢙ
ꢟ
ꢞ
ꢝ
ꢠ
ꢠ
ꢠ
ꢙ
ꢛ
ꢚ
ꢤ
ꢢ
ꢥ
ꢠ
ꢠ
ꢦ
ꢘ
ꢡ
ꢞ
ꢠ
ꢟ
ꢘ
ꢟ
ꢬ
ꢛ
ꢜ
ꢙ
ꢢ
ꢧ
ꢞ
ꢙ
ꢧ
ꢟ
ꢟ
ꢣ
ꢠ
ꢣ
ꢨ
Copyright 2003, Texas Instruments Incorporated
ꢉ ꢙ ꢤ ꢜ ꢛꢧ ꢢꢡ ꢟꢠ ꢡꢛ ꢝꢤ ꢦꢘ ꢞꢙ ꢟ ꢟꢛ ꢮꢒ ꢌꢐ ꢔꢑ ꢕ ꢐꢆꢯꢂ ꢆꢂꢈ ꢞꢦꢦ ꢤꢞ ꢜ ꢞ ꢝꢣ ꢟꢣꢜ ꢠ ꢞ ꢜ ꢣ ꢟꢣ ꢠꢟꢣ ꢧ
ꢜ
ꢛ
ꢡ
ꢟ
ꢛ
ꢜ
ꢝ
ꢟ
ꢛ
ꢠ
ꢤ
ꢘ
ꢚ
ꢘ
ꢡ
ꢣ
ꢜ
ꢟ
ꢩ
ꢟ
ꢣ
ꢜ
ꢛ
ꢚ
ꢊ
ꢣ
ꢪ
ꢞ
ꢒ
ꢙ
ꢝ
ꢣ
ꢠ
ꢟ
ꢞ
ꢙ
ꢧ
ꢜ
ꢧ
ꢞ
ꢟ ꢣ ꢠ ꢟꢘ ꢙꢭ ꢛꢚ ꢞ ꢦꢦ ꢤꢞ ꢜ ꢞ ꢝ ꢣ ꢟ ꢣ ꢜ ꢠ ꢨ
ꢜ
ꢞ
ꢙ
ꢟ
ꢬ
ꢨ
ꢔ
ꢜ
ꢛ
ꢧ
ꢟ
ꢘ
ꢛ
ꢡ
ꢣ
ꢠ
ꢘ
ꢙ
ꢭ
ꢧ
ꢛ
ꢣ
ꢛ
ꢟ
ꢙ
ꢣ
ꢡ
ꢣ
ꢠ
ꢞ
ꢜ
ꢘ
ꢦ
ꢘ
ꢙ
ꢡ
ꢦ
ꢢ
ꢢ ꢙꢦ ꢣꢠꢠ ꢛ ꢟꢩꢣ ꢜ ꢫꢘ ꢠꢣ ꢙ ꢛꢟꢣ ꢧꢨ ꢉ ꢙ ꢞꢦ ꢦ ꢛ ꢟꢩꢣ ꢜ ꢤꢜ ꢛ ꢧꢢꢡ ꢟꢠ ꢈ ꢤꢜ ꢛ ꢧꢢꢡ ꢟꢘꢛ ꢙ
ꢟ
ꢤ
ꢜ
ꢛ
ꢡ
ꢣ
ꢠ
ꢠ
ꢘ
ꢙ
ꢭ
ꢧ
ꢛ
ꢣ
ꢠ
ꢙ
ꢛ
ꢟ
ꢙ
ꢣ
ꢡ
ꢣ
ꢠ
ꢠ
ꢞ
ꢜ
ꢘ
ꢦ
ꢬ
ꢘ
ꢙ
ꢡ
ꢦ
ꢢ
ꢧ
ꢣ
ꢟ
ꢣ
ꢠ
ꢘ
ꢙ
ꢭ
ꢛ
ꢚ
ꢞ
ꢦ
ꢦ
ꢤ
ꢞ
ꢜ
ꢞ
ꢝꢣ
ꢟ
ꢣ
ꢜ
ꢠ
ꢨ
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265