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SN54HC259 PDF预览

SN54HC259

更新时间: 2024-01-26 07:10:55
品牌 Logo 应用领域
TAOS 锁存器双倍数据速率
页数 文件大小 规格书
20页 828K
描述
8-BIT ADDRESSABLE LATCHES

SN54HC259 技术参数

生命周期:Obsolete零件包装代码:QLCC
包装说明:QCCN,针数:20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.62其他特性:1:8 DMUX FOLLOWED BY LATCH; RESET ACTIVE ONLY WHEN LATCH ENABLE IS HIGH
系列:HC/UHJESD-30 代码:S-CQCC-N20
长度:8.89 mm负载电容(CL):50 pF
逻辑集成电路类型:D LATCH位数:1
功能数量:1端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:TRUE封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:QCCN封装形状:SQUARE
封装形式:CHIP CARRIER传播延迟(tpd):195 ns
认证状态:Not Qualified座面最大高度:2.03 mm
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子形式:NO LEAD端子节距:1.27 mm
端子位置:QUAD触发器类型:LOW LEVEL
宽度:8.89 mmBase Number Matches:1

SN54HC259 数据手册

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ꢀꢁꢂ ꢃ ꢄꢅ ꢆ ꢂꢇ ꢈ ꢀꢁꢉ ꢃꢄ ꢅꢆ ꢂꢇ  
ꢊ ꢋꢌꢍ ꢎ ꢏꢐꢐ ꢑꢒꢀꢀ ꢏꢌꢓ ꢒ ꢓꢏꢎꢅ ꢄ ꢒꢀ  
SCLS134E − DECEMBER 1982 − REVISED SEPTEMBER 2003  
SN54HC259 . . . J OR W PACKAGE  
SN74HC259 . . . D, N, NS, OR PW PACKAGE  
(TOP VIEW)  
D
D
Wide Operating Voltage Range of 2 V to 6 V  
High-Current Inverting Outputs Drive Up To  
10 LSTTL Loads  
D
D
D
D
D
Low Power Consumption, 80-µA Max I  
Typical t = 14 ns  
pd  
4-mA Output Drive at 5 V  
CC  
S0  
S1  
S2  
Q0  
Q1  
Q2  
Q3  
GND  
1
2
3
4
5
6
7
8
16  
V
CC  
15 CLR  
14  
13  
12  
11  
10  
9
G
D
Q7  
Q6  
Q5  
Q4  
Low Input Current of 1 µA Max  
8-Bit Parallel-Out Storage Register  
Performs Serial-to-Parallel Conversion With  
Storage  
D
D
D
D
D
Asynchronous Parallel Clear  
Active-High Decoder  
SN54HC259 . . . FK PACKAGE  
(TOP VIEW)  
Enable Input Simplifies Expansion  
Expandable for n-Bit Applications  
Four Distinct Functional Modes  
3
2
1
20 19  
18  
S2  
Q0  
NC  
Q1  
Q2  
G
4
5
6
7
8
description/ordering information  
17  
16  
15  
14  
D
NC  
Q7  
Q6  
These 8-bit addressable latches are designed for  
general-purpose storage applications in digital  
systems. Specific uses include working registers,  
serial-holding registers, and active-high decoders  
or demultiplexers. They are multifunctional  
devices capable of storing single-line data in eight  
addressable latches and being a 1-of-8 decoder  
or demultiplexer with active-high outputs.  
9 10 11 12 13  
NC − No internal connection  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP − N  
SOIC − D  
Tube of 25  
Tube of 40  
Reel of 2500  
Reel of 250  
Reel of 2000  
Reel of 2000  
Reel of 250  
Tube of 25  
Tube of 150  
Tube of 55  
SN74HC259N  
SN74HC259N  
SN74HC259D  
SN74HC259DR  
SN74HC259DT  
SN74HC259NSR  
SN74HC259PWR  
SN74HC259PWT  
SNJ54HC259J  
SNJ54HC259W  
SNJ54HC259FK  
HC259  
−40°C to 85°C  
SOP − NS  
HC259  
HC259  
TSSOP − PW  
CDIP − J  
CFP − W  
LCCC − FK  
SNJ54HC259J  
SNJ54HC259W  
SNJ54HC259FK  
−55°C to 125°C  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
ꢕ ꢘ ꢣ ꢛ ꢚꢦ ꢡꢠ ꢞꢟ ꢠꢚ ꢜꢣ ꢥꢗ ꢝꢘ ꢞ ꢞꢚ ꢭꢍ ꢓꢋ ꢔꢑ ꢮ ꢋꢯꢊꢂ ꢯꢂꢈ ꢝꢥꢥ ꢣꢝ ꢛ ꢝ ꢜꢢ ꢞꢢꢛ ꢟ ꢝ ꢛ ꢢ ꢞꢢ ꢟꢞꢢ ꢦ  
ꢞ ꢢ ꢟ ꢞꢗ ꢘꢬ ꢚꢙ ꢝ ꢥꢥ ꢣꢝ ꢛ ꢝ ꢜ ꢢ ꢞ ꢢ ꢛ ꢟ ꢧ  
ꢡ ꢘꢥ ꢢꢟꢟ ꢚ ꢞꢨꢢ ꢛ ꢪꢗ ꢟꢢ ꢘ ꢚꢞꢢ ꢦꢧ ꢕ ꢘ ꢝꢥ ꢥ ꢚ ꢞꢨꢢ ꢛ ꢣꢛ ꢚ ꢦꢡꢠ ꢞꢟ ꢈ ꢣꢛ ꢚ ꢦꢡꢠ ꢞꢗꢚ ꢘ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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