Datasheet > SN54HC259_16

SN54HC259_16

更新时间： 2024-10-01 02:58:19

品牌	Logo	应用领域
德州仪器 - TI		双倍数据速率
页数	文件大小	规格书
9页	137K
描述
8-BIT ADDRESSABLE LATCHES

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数据手册

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SN54HC259_16 数据手册

SN54HC259, SN74HC259

8-BIT ADDRESSABLE LATCHES

SCLS134B – DECEMBER 1982 – REVISED MAY 1997

SN54HC259 . . . J OR W PACKAGE

SN74HC259 . . . D, N, OR PW PACKAGE

(TOP VIEW)

8-Bit Parallel-Out Storage Register

Performs Serial-to-Parallel Conversion With

Storage

Asynchronous Parallel Clear

Active-High Decoder

GND

CLR

Enable Input Simplifies Expansion

Expandable for n-Bit Applications

Four Distinct Functional Modes

Package Options Include Plastic

Small-Outline (D), Thin Shrink

Small-Outline (PW), and Ceramic Flat (W)

Packages, Ceramic Chip Carriers (FK), and

Standard Plastic (N) and Ceramic (J)

300-mil DIPs

SN54HC259 . . . FK PACKAGE

(TOP VIEW)

description

These 8-bit addressable latches are designed for

general-purpose storage applications in digital

systems. Specific uses include working registers,

serial-holding registers, and active-high decoders

or demultiplexers. They are multifunctional

devices capable of storing single-line data in eight

addressable latches, and being a 1-of-8 decoder

or demultiplexer with active-high outputs.

20 19

9 10 11 12 13

Four distinct modes of operation are selectable by

controlling the clear (CLR) and enable (G) inputs.

In the addressable-latch mode, data at the data-in

terminal is written into the addressed latch. The

addressed latch follows the data input with all

unaddressed latches remaining in their previous

states. In the memory mode, all latches remain in

their previous states and are unaffected by the

data or address inputs. To eliminate the possibility

of entering erroneous data in the latches, G

should be held high (inactive) while the address

lines are changing. In the 1-of-8 decoding or

demultiplexing mode, the addressed output

follows the level of the D input with all other

outputs low. In the clear mode, all outputs are low

and unaffected by the address and data inputs.

NC – No internal connection

The SN54HC259 is characterized for operation over the full military temperature range of –55°C to 125°C. The

SN74HC259 is characterized for operation from –40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...9

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与SN54HC259_16相关器件

型号	品牌	获取价格	描述	数据表
SN54HC259FH	ROCHESTER	获取价格	D Latch
SN54HC259FK	TI	获取价格	8-BIT ADDRESSABLE LATCHES
SN54HC259FK-00	TI	获取价格	HC/UH SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, CQCC20
SN54HC259FKR	TI	获取价格	HC/UH SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, CQCC20, CERAMIC, LCC-20
SN54HC259J	TI	获取价格	8-BIT ADDRESSABLE LATCHES
SN54HC259J-00	TI	获取价格	HC/UH SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, CDIP16
SN54HC259W	TI	获取价格	8-BIT ADDRESSABLE LATCHES
SN54HC266	TI	获取价格	QUADRUPLE 2-INPUT EXCLUSIVE-NOR GATES WITH OPEN-DRAIN OUTPUTS
SN54HC266_07	TI	获取价格	QUADRUPLE 2-INPUT EXCLUSIVE-NOR GATES WITH OPEN-DRAIN OUTPUTS
SN54HC266FH	TI	获取价格	IC,LOGIC GATE,QUAD 2-INPUT XNOR,HC-CMOS,LLCC,20PIN,CERAMIC

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