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SN54HC266J PDF预览

SN54HC266J

更新时间: 2024-09-29 23:03:03
品牌 Logo 应用领域
德州仪器 - TI 输出元件输入元件
页数 文件大小 规格书
4页 80K
描述
QUADRUPLE 2-INPUT EXCLUSIVE-NOR GATES WITH OPEN-DRAIN OUTPUTS

SN54HC266J 技术参数

生命周期:Obsolete零件包装代码:DIP
包装说明:DIP, DIP14,.3针数:14
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.47
系列:HC/UHJESD-30 代码:R-GDIP-T14
长度:19.56 mm负载电容(CL):50 pF
逻辑集成电路类型:XNOR GATE最大I(ol):0.004 A
功能数量:4输入次数:2
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C输出特性:OPEN-DRAIN
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装等效代码:DIP14,.3封装形状:RECTANGULAR
封装形式:IN-LINE电源:2/6 V
Prop。Delay @ Nom-Sup:38 ns传播延迟(tpd):190 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:5.08 mm子类别:Gates
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL宽度:7.62 mm
Base Number Matches:1

SN54HC266J 数据手册

 浏览型号SN54HC266J的Datasheet PDF文件第2页浏览型号SN54HC266J的Datasheet PDF文件第3页浏览型号SN54HC266J的Datasheet PDF文件第4页 
SN54HC266, SN74HC266  
QUADRUPLE 2-INPUT EXCLUSIVE-NOR GATES  
WITH OPEN-DRAIN OUTPUTS  
SCLS135C – DECEMBER 1982 – REVISED MAY 1997  
SN54HC266 . . . J OR W PACKAGE  
SN74HC266 . . . D OR N PACKAGE  
(TOP VIEW)  
Package Options Include Plastic  
Small-Outline (D) and Ceramic Flat (W)  
Packages, Ceramic Chip Carriers (FK), and  
Standard Plastic (N) and Ceramic (J)  
300-mil DIPs  
1A  
1B  
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
4B  
4A  
4Y  
1Y  
description  
2Y  
The ’HC266 are composed of four independent  
2-input exclusive-NOR gates and feature  
open-drain outputs. They perform the Boolean  
function Y = A B or Y = AB + AB in positive logic.  
2A  
10 3Y  
9
8
2B  
3B  
3A  
GND  
The SN54HC266 is characterized for operation  
over the full military temperature range of –55°C  
to 125°C. The SN74HC266 is characterized for  
operation from –40°C to 85°C.  
SN54HC266 . . . FK PACKAGE  
(TOP VIEW)  
3
2
1
20 19  
18  
4A  
NC  
4Y  
1Y  
NC  
2Y  
FUNCTION TABLE  
4
5
6
7
8
17  
16  
INPUTS  
OUTPUT  
Y
A
B
L
15 NC  
14  
9 10 11 12 13  
NC  
2A  
L
L
H
L
3Y  
H
L
H
H
L
H
H
NC – No internal connection  
logic symbol  
1
1A  
2
=1  
3
1Y  
1B  
5
2A  
6
4
2Y  
2B  
8
3A  
9
10  
3Y  
3B  
12  
13  
4A  
4B  
11  
4Y  
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.  
Pin numbers shown are for the D, J, N, and W packages.  
logic diagram, each gate (positive logic)  
A
B
Y
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1997, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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