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SN54HC195J-00 PDF预览

SN54HC195J-00

更新时间： 2024-11-05 19:23:39
品牌 Logo 应用领域
德州仪器 - TI 输入元件输出元件逻辑集成电路触发器
页数 文件大小 规格书
10页 219K
描述
HC/UH SERIES, 4-BIT RIGHT PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CDIP16

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SN54HC195J-00 技术参数

生命周期：Obsolete包装说明：DIP,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.37其他特性：COMPLEMENTARY SERIAL SHIFT RIGHT OUTPUT; J AND KBAR SERIAL INPUT
计数方向：RIGHT系列：HC/UH
JESD-30 代码：R-GDIP-T16长度：19.56 mm
负载电容（CL）：50 pF逻辑集成电路类型：PARALLEL IN PARALLEL OUT
位数：4功能数量：1
端子数量：16最高工作温度：125 °C
最低工作温度：-55 °C输出极性：TRUE
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DIP
封装形状：RECTANGULAR封装形式：IN-LINE
传播延迟（tpd）：44 ns认证状态：Not Qualified
座面最大高度：5.08 mm最大供电电压 (Vsup)：6 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：5 V
表面贴装：NO技术：CMOS
温度等级：MILITARY端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
触发器类型：POSITIVE EDGE宽度：7.62 mm
最小 fmax：21 MHzBase Number Matches：1

SN54HC195J-00 数据手册

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SN54HC195  
4-BIT PARALLEL-ACCESS SHIFT REGISTERS  
www.ti.com  
SCLS124A–DECEMBER 1992–REVISED NOVEMBER 2007  
1
FEATURES  
SN54HC195 . . . J PACKAGE  
(TOP VIEW)  
•
Synchronous Parallel Load  
•
•
•
•
Positive-Edge-Triggered Clocking  
J and K Inputs to First Stage  
CLR  
J
VCC  
QA  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
Complementary Outputs From Last Stage  
K
QB  
Package Options: Plastic and Ceramic DIPS  
and Ceramic Chip Carriers  
A
QC  
B
12 QD  
11  
•
Dependable Texas lnstruments Quality and  
Reliability  
C
QD  
10  
9
D
CLK  
GND  
SH/LD  
DESCRIPTION/ORDERING INFORMATION  
These 4-bit registers feature parallel inputs, parallel  
outputs, J-K serial inputs, shift/load control input, and  
a direct overriding clear. The registers have two  
modes of operation: parallel (broadside) load, and  
shift (in the direction QA and QD).  
SN54HC195 . . . FK PACKAGE  
(TOP VIEW)  
3
2
1
20 19  
18  
Parallel loading is accomplished by applying the  
4-bits of data and taking the shift/load control input  
low. The data is loaded into the associated flip-flop  
and appears at the outputs after the positive  
transition of the clock input. During loading, serial  
data flow is inhibited.  
QB  
QC  
NC  
QD  
QD  
K
A
4
5
6
7
8
17  
16  
15  
14  
NC  
B
C
9 10 11 12 13  
Shifting is accomplished synchronously when the  
shift/load control input is high. Serial data for this  
mode is entered at the J-K inputs. These inputs  
permit the first stage to perform as a J-K, D, or T type  
flip-flop as shown in the function table.  
NC − No internal connection  
LOGIC SYMBOL†  
The SN54HC195 is characterized for operation over  
the full military temperature range of –55°C to 125°C.  
(1)  
SRG4  
R
CLR  
(9)  
SH/LD  
M1 (SHIFT)  
M2 (LOAD)  
C3/1  
(10)  
CLK  
(2)  
(3)  
(4)  
(5)  
(6)  
(7)  
J
K
A
1,3J  
1,3K  
2,3D  
2,3D  
(15)  
(14)  
(13)  
(12)  
(11)  
Q
Q
Q
A
B
C
B
C
D
Q
Q
D
D
†
This symbol is in accordance with ANSI/IEEE Std 91−1984  
and IEC Publication 617−12.  
Pin numbers shown are for J package.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1992–2007, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...10

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