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SN54HC112_14

更新时间： 2024-09-14 02:58:43
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德州仪器 - TI /
页数 文件大小 规格书
14页 445K
描述
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

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SN54HC112_14 数据手册

 浏览型号SN54HC112_14的Datasheet PDF文件第2页浏览型号SN54HC112_14的Datasheet PDF文件第3页浏览型号SN54HC112_14的Datasheet PDF文件第4页浏览型号SN54HC112_14的Datasheet PDF文件第5页浏览型号SN54HC112_14的Datasheet PDF文件第6页浏览型号SN54HC112_14的Datasheet PDF文件第7页 
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ꢚ ꢔꢓ ꢄ ꢅꢍ ꢑꢌꢖ ꢌꢁꢊ ꢘ ꢖꢑ ꢀ ꢑꢓ  
SCLS099F − DECEMBER 1982 − REVISED SEPTEMBER 2003  
SN54HC112 . . . J OR W PACKAGE  
SN74HC112 . . . D OR N PACKAGE  
(TOP VIEW)  
D
D
D
D
D
D
Wide Operating Voltage Range of 2 V to 6 V  
Outputs Can Drive Up To 10 LSTTL Loads  
Low Power Consumption, 40-µA Max I  
CC  
1CLK  
1K  
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
Typical t = 13 ns  
pd  
4-mA Output Drive at 5 V  
1CLR  
2CLR  
2CLK  
1J  
Low Input Current of 1 µA Max  
1PRE  
1Q  
12 2K  
description/ordering information  
11  
10  
9
1Q  
2J  
2Q  
2PRE  
2Q  
The ’HC112 devices contain two independent J-K  
negative-edge-triggered flip-flops. A low level at  
the preset (PRE) or clear (CLR) inputs sets or  
resets the outputs, regardless of the levels of the  
other inputs. When PRE and CLR are inactive  
(high), data at the J and K inputs meeting the  
setup time requirements are transferred to the  
outputs on the negative-going edge of the clock  
(CLK) pulse. Clock triggering occurs at a voltage  
level and is not directly related to the fall time of the  
CLK pulse. Following the hold-time interval, data  
at the J and K inputs may be changed without  
affecting the levels at the outputs. These versatile  
flip-flops perform as toggle flip-flops by tying J and  
K high.  
GND  
SN54HC112 . . . FK PACKAGE  
(TOP VIEW)  
3
2
1
20 19  
18  
2CLR  
2CLK  
NC  
1J  
1PRE  
NC  
4
5
6
7
8
17  
16  
15 2K  
14  
9 10 11 12 13  
1Q  
2J  
1Q  
NC − No internal connection  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP − N  
SOIC − D  
Tube of 25  
Tube of 40  
Reel of 2500  
Reel of 250  
Tube of 25  
Tube of 150  
Tube of 55  
SN74HC112N  
SN74HC112N  
SN74HC112D  
−40°C to 85°C  
SN74HC112DR  
SN74HC112DT  
SNJ54HC112J  
SNJ54HC112W  
SNJ54HC112FK  
HC112  
CDIP − J  
CFP − W  
LCCC − FK  
SNJ54HC112J  
−55°C to 125°C  
SNJ54HC112W  
SNJ54HC112FK  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
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Copyright 2003, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...14

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与SN54HC112_14相关器件

型号 品牌 获取价格 描述 数据表
SN54HC112FH TI

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 		IC,FLIP-FLOP,DUAL,J/K TYPE,HC-CMOS,LLCC,20PIN,CERAMIC
SN54HC112FK TI

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 		DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
SN54HC112FK-00 TI

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 		HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CQCC20
SN54HC112FKR TI

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 		HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CQCC20, CE
SN54HC112J TI

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 		DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
SN54HC112J-00 TI

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 		HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16
SN54HC112W TI

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 		DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
SN54HC112WR TI

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 		HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP16, CE
SN54HC114 TI

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 		DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET, COMMON CLEAR, AND COMMON CLOCK
SN54HC114J TI

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 		IC,FLIP-FLOP,DUAL,J/K TYPE,HC-CMOS,DIP,14PIN,CERAMIC

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