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SN54AS823A_15

更新时间： 2024-11-16 02:58:39
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德州仪器 - TI 输出元件
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9-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

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SN54AS823A_15 数据手册

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SN54AS823A, SN74AS823A, SN74AS824A  
9-BIT BUS-INTERFACE FLIP-FLOPS  
WITH 3-STATE OUTPUTS  
SDAS231A – JUNE 1984 – REVISED AUGUST 1995  
SN54AS823A . . . JT PACKAGE  
SN74AS823A . . . DW OR NT PACKAGE  
(TOP VIEW)  
• Functionally Equivalent to AMD’s AM29823  
and AM29824  
• Provide Extra Data Width Necessary for  
Wider Address/Data Paths or Buses With  
Parity  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
V
CC  
1
2
3
4
5
6
7
8
9
24  
23 1Q  
22 2Q  
21 3Q  
20 4Q  
19 5Q  
18 6Q  
17 7Q  
16 8Q  
15 9Q  
14 CLKEN  
13 CLK  
• Outputs Have Undershoot-Protection  
Circuitry  
• Power-Up High-Impedance State  
• Buffered Control Inputs to Reduce  
dc Loading Effects  
• Package Options Include Plastic  
Small-Outline (DW) Packages, Ceramic  
Chip Carriers (FK), and Standard Plastic  
(NT) and Ceramic (JT) 300-mil DIPs  
9D 10  
CLR 11  
GND 12  
description  
SN54AS823A . . . FK PACKAGE  
(TOP VIEW)  
These 9-bit flip-flops feature 3-state outputs  
designed specifically for driving highly capacitive  
or relatively low-impedance loads. These devices  
are particularly suitable for implementing wider  
buffer registers, I/O ports, bidirectional bus  
drivers, parity bus interfacing, and working  
registers.  
4
3
2
1
28 27 26  
25  
3D  
4D  
5D  
NC  
6D  
7D  
8D  
3Q  
4Q  
5Q  
NC  
6Q  
7Q  
8Q  
5
24  
23  
22  
21  
20  
19  
6
7
With the clock-enable (CLKEN) input low, the nine  
D-type edge-triggered flip-flops enter data on the  
low-to-high transitions of the clock (CLK) input.  
Taking CLKEN high disables the clock buffer,  
latching the outputs. The SN54AS823A and  
SN74AS823A have noninverting data (D) inputs  
and the SN74AS824A has inverting (D) inputs.  
Taking the clear (CLR) input low causes the nine  
Q outputs to go low independently of the clock.  
8
9
10  
11  
12 13 14 15 16 17 18  
SN74AS824A . . . DW OR NT PACKAGE  
(TOP VIEW)  
A buffered output-enable (OE) input can be used  
to place the nine outputs in either a normal logic  
state (high or low logic level) or the high-  
impedance state. In the high-impedance state, the  
outputs neither load nor drive the bus lines  
significantly. The high-impedance state and  
increased drive provide the capability to drive bus  
lines without interface or pullup components.  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
1
2
3
4
5
6
7
8
9
24  
V
CC  
23 1Q  
22 2Q  
21 3Q  
20 4Q  
19 5Q  
18 6Q  
17 7Q  
16 8Q  
15 9Q  
14 CLKEN  
13 CLK  
OE does not affect the internal operation of the  
flip-flops. Old data can be retained or new data  
can be entered while the outputs are in the  
high-impedance state.  
9D 10  
CLR 11  
GND 12  
The SN54AS823A is characterized for operation  
over the full military temperature range of –55°C  
to 125°C. The SN74AS823A and SN74AS824A  
are characterized for operation from 0°C to 70°C.  
NC – No internal connection  
Copyright 1995, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567

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SN54AS823AJT TI

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SN54AS823FH TI

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SN54AS823JT TI

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 		9-Bit Bus Interface Flip-Flops With 3-State Outputs 24-CDIP -55 to 125
SN54AS823JT-00 TI

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 		AS SERIES, 9-BIT DRIVER, TRUE OUTPUT, CDIP24
SN54AS824FH TI

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 		IC,FLIP-FLOP,9-BIT,D TYPE,AS-TTL,LLCC,28PIN,CERAMIC
SN54AS824FH-00 TI

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 		AS SERIES, 9-BIT DRIVER, INVERTED OUTPUT, CQCC28
SN54AS824FK TI

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 		IC AS SERIES, 9-BIT DRIVER, INVERTED OUTPUT, CQCC28, CERAMIC, CC-28, Bus Driver/Transceive
SN54AS824JT TI

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 		AS SERIES, 9-BIT DRIVER, INVERTED OUTPUT, CDIP24, 0.300 INCH, CERAMIC, DIP-24

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