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SN54AS825AJT

更新时间： 2024-09-29 22:35:39
品牌 Logo 应用领域
德州仪器 - TI 触发器输出元件
页数 文件大小 规格书
7页 108K
描述
8-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

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SN54AS825AJT 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：DIP
包装说明：DIP, DIP24,.3针数：24
Reach Compliance Code：not_compliantHTS代码：8542.39.00.01
风险等级：5.5其他特性：WITH TRIPLE OUTPUT ENABLE; WITH CLEAR AND CLOCK ENABLE
系列：ASJESD-30 代码：R-GDIP-T24
长度：32.005 mm负载电容（CL）：50 pF
逻辑集成电路类型：BUS DRIVER最大频率@ Nom-Sup：52600000 Hz
最大I（ol）：0.032 A位数：8
功能数量：1端口数量：2
端子数量：24最高工作温度：125 °C
最低工作温度：-55 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：CERAMIC, GLASS-SEALED
封装代码：DIP封装等效代码：DIP24,.3
封装形状：RECTANGULAR封装形式：IN-LINE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
最大电源电流（ICC）：90 mA传播延迟（tpd）：13.5 ns
认证状态：Not Qualified座面最大高度：5.08 mm
子类别：FF/Latches最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：NO技术：TTL
温度等级：MILITARY端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED触发器类型：POSITIVE EDGE
宽度：7.62 mmBase Number Matches：1

SN54AS825AJT 数据手册

 浏览型号SN54AS825AJT的Datasheet PDF文件第2页浏览型号SN54AS825AJT的Datasheet PDF文件第3页浏览型号SN54AS825AJT的Datasheet PDF文件第4页浏览型号SN54AS825AJT的Datasheet PDF文件第5页浏览型号SN54AS825AJT的Datasheet PDF文件第6页浏览型号SN54AS825AJT的Datasheet PDF文件第7页 
SN54AS825A, SN74AS825A  
8-BIT BUS-INTERFACE FLIP-FLOPS  
WITH 3-STATE OUTPUTS  
SDAS020B – JUNE 1984 – REVISED AUGUST 1995  
SN54AS825A . . . JT PACKAGE  
SN74AS825A . . . DW OR NT PACKAGE  
(TOP VIEW)  
• Functionally Equivalent to AMD’s AM29825  
• Improved I Specifications  
OH  
• Multiple Output Enables Allow Multiuser  
Control of the Interface  
OE1  
OE2  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
V
CC  
1
2
3
4
5
6
7
8
9
24  
23 OE3  
22 1Q  
21 2Q  
20 3Q  
19 4Q  
18 5Q  
17 6Q  
16 7Q  
15 8Q  
14 CLKEN  
13 CLK  
• Outputs Have Undershoot-Protection  
Circuitry  
• Power-Up High-Impedance State  
• Buffered Control Inputs Reduce dc  
Loading Effects  
• Package Options Include Plastic  
Small-Outline (DW) Packages, Ceramic  
Chip Carriers (FK), and Standard Plastic  
(NT) and Ceramic (JT) 300-mil DIPs  
8D 10  
CLR 11  
GND 12  
description  
These 8-bit flip-flops feature 3-state outputs  
designed specifically for driving highly capacitive  
or relatively low-impedance loads. These devices  
are particularly suitable for implementing  
multiuser registers, I/O ports, bidirectional bus  
drivers, and working registers.  
SN54AS825A . . . FK PACKAGE  
(TOP VIEW)  
4
3
2
1
28 27 26  
25  
2D  
3D  
4D  
NC  
5D  
6D  
7D  
2Q  
3Q  
4Q  
NC  
5Q  
6Q  
7Q  
5
With the clock-enable (CLKEN) input low, the  
eight D-type edge-triggered flip-flops enter data  
on the low-to-high transitions of the clock (CLK)  
input. Taking CLKEN high disables the clock  
buffer, latching the outputs. These devices have  
noninverting data (D) inputs. Taking the clear  
(CLR) input low causes the eight Q outputs to go  
low independently of the clock.  
24  
23  
22  
21  
20  
19  
6
7
8
9
10  
11  
12 13 14 15 16 17 18  
Multiuser buffered output-enable (OE1, OE2, and  
OE3) inputs can be used to place the eight outputs  
in either a normal logic state (high or low logic  
NC – No internal connection  
level) or  
a high-impedance state. In the  
high-impedance state, the outputs neither load  
nor drive the bus lines significantly. The high-  
impedance state and increased drive provide the  
capability to drive bus lines without interface or  
pullup components.  
The output enables do not affect the internal operation of the flip-flops. Old data can be retained or new data  
can be entered while the outputs are in the high-impedance state.  
The SN54AS825A is characterized for operation over the full military temperature range of –55°C to 125°C. The  
SN74AS825A is characterized for operation from 0°C to 70°C.  
Copyright 1995, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567

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