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SN54AS169AFK PDF预览

SN54AS169AFK

更新时间： 2024-09-30 22:59:15
品牌 Logo 应用领域
德州仪器 - TI 计数器触发器逻辑集成电路输出元件
页数 文件大小 规格书
9页 150K
描述
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS

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SN54AS169AFK 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFN包装说明：CERAMIC, CC-20
针数：20Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01风险等级：5.92
Is Samacsys：N其他特性：TCO OUTPUT
计数方向：BIDIRECTIONAL系列：AS
JESD-30 代码：S-CQCC-N20长度：8.89 mm
负载电容（CL）：50 pF负载/预设输入：YES
逻辑集成电路类型：BINARY COUNTER最大频率@ Nom-Sup：65000000 Hz
最大I（ol）：0.02 A工作模式：SYNCHRONOUS
位数：4功能数量：1
端子数量：20最高工作温度：125 °C
最低工作温度：-55 °C封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：QCCN封装等效代码：LCC20,.35SQ
封装形状：SQUARE封装形式：CHIP CARRIER
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
最大电源电流（ICC）：63 mA传播延迟（tpd）：14 ns
认证状态：Not Qualified座面最大高度：2.03 mm
子类别：Counters最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：TTL
温度等级：MILITARY端子形式：NO LEAD
端子节距：1.27 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED触发器类型：POSITIVE EDGE
宽度：8.89 mm最小 fmax：60 MHz
Base Number Matches：1

SN54AS169AFK 数据手册

 浏览型号SN54AS169AFK的Datasheet PDF文件第2页浏览型号SN54AS169AFK的Datasheet PDF文件第3页浏览型号SN54AS169AFK的Datasheet PDF文件第4页浏览型号SN54AS169AFK的Datasheet PDF文件第5页浏览型号SN54AS169AFK的Datasheet PDF文件第6页浏览型号SN54AS169AFK的Datasheet PDF文件第7页 
SN54ALS169B, SN54AS169A, SN74ALS169B, SN74AS169A  
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS  
SDAS125B – MARCH 1984 – REVISED DECEMBER 1994  
SN54ALS169B, SN54AS169A . . . J PACKAGE  
SN74ALS169B, SN74AS169A . . . D OR N PACKAGE  
(TOP VIEW)  
• Fully Synchronous Operation for Counting  
and Programming  
• Internal Carry Look-Ahead Circuitry for  
Fast Counting  
U/D  
CLK  
A
V
CC  
RCO  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
• Carry Output for n-Bit Cascading  
• Fully Independent Clock Circuit  
• Package Options Include Plastic  
Small-Outline (D) Packages, Ceramic Chip  
Carriers (FK), and Standard Plastic (N) and  
Ceramic (J) 300-mil DIPs  
Q
A
B
C
D
Q
B
Q
C
Q
D
ENT  
ENP  
GND  
LOAD  
description  
SN54ALS169B, SN54AS169A . . . FK PACKAGE  
(TOP VIEW)  
These synchronous 4-bit up/down binary  
presettable counters feature an internal carry  
look-ahead circuitry for cascading in high-speed  
counting applications. Synchronous operation is  
provided by having all flip-flops clocked  
simultaneously so that the outputs change  
coincident with each other when so instructed by  
the count-enable (ENP, ENT) inputs and internal  
gating. This mode of operation eliminates the  
output counting spikes normally associated with  
asynchronous (ripple-clock) counters. A buffered  
clock (CLK) input triggers the four flip-flops on the  
rising(positive-going)edgeoftheclockwaveform.  
3
2
1
20 19  
18  
A
B
Q
Q
4
5
6
7
8
A
B
17  
16  
15  
14  
NC  
C
NC  
Q
C
D
Q
D
9 10 11 12 13  
These counters are fully programmable; that is,  
they may be preset to either level. The load-input  
circuitry allows loading with the carry-enable  
output of cascaded counters. Because loading is  
synchronous, setting up a low level at the load  
(LOAD) input disables the counter and causes the  
outputs to agree with the data inputs after the next  
clock pulse.  
NC – No internal connection  
The internal carry look-ahead circuitry provides for cascading counters for n-bit synchronous application without  
additional gating. ENP and ENT inputs and a ripple-carry output (RCO) are instrumental in accomplishing this  
function. Both ENP and ENT must be low to count. The direction of the count is determined by the level of the  
up/down (U/D) input. When U/D is high, the counter counts up; when low, it counts down. ENT is fed forward  
to enable RCO. RCO, thus enabled, produces a low-level pulse while the count is zero (all inputs low) counting  
down or maximum (15) counting up. This low-level overflow ripple-carry pulse can be used to enablesuccessive  
cascaded stages. Transitions at ENP or ENT are allowed regardless of the level of the clock input. All inputs  
are diode clamped to minimize transmission-line effects, thereby simplifying system design.  
These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, LOAD, or U/D)  
that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function  
of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the  
stable setup and hold times.  
The SN54ALS169B and SN54AS169A are characterized for operation over the full military temperature range  
of –55°C to 125°C. The SN74ALS169B and SN74AS169A are characterized for operation from 0°C to 70°C.  
Copyright 1994, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
2–1  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

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与SN54AS169AFK相关器件

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SN54AS169AJ TI

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 		SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS
SN54AS169FH TI

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 		IC,COUNTER,UP/DOWN,4-BIT BINARY,AS-TTL,LLCC,20PIN,CERAMIC
SN54AS169FH-00 TI

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 		AS SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, CQCC20
SN54AS169J TI

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 		AS SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, CDIP16
SN54AS169J-00 TI

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 		AS SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, CDIP16
SN54AS174 TI

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 		HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
SN54AS174FH TI

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 		IC,FLIP-FLOP,HEX,D TYPE,AS-TTL,LLCC,20PIN,CERAMIC
SN54AS174FK TI

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 		HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
SN54AS174J TI

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 		HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
SN54AS174J-00 TI

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 		AS SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CDIP16

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