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SN54AS163FK PDF预览

SN54AS163FK

更新时间： 2024-11-23 22:19:35
品牌 Logo 应用领域
德州仪器 - TI 计数器触发器逻辑集成电路输出元件
页数 文件大小 规格书
14页 222K
描述
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS

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SN54AS163FK 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QLCC包装说明：QCCN, LCC20,.35SQ
针数：20Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01风险等级：5.91
其他特性：TCO OUTPUT计数方向：UP
系列：ASJESD-30 代码：S-CQCC-N20
长度：8.89 mm负载电容（CL）：50 pF
负载/预设输入：YES逻辑集成电路类型：BINARY COUNTER
最大频率@ Nom-Sup：65000000 Hz最大I（ol）：0.02 A
工作模式：SYNCHRONOUS位数：4
功能数量：1端子数量：20
最高工作温度：125 °C最低工作温度：-55 °C
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：QCCN
封装等效代码：LCC20,.35SQ封装形状：SQUARE
封装形式：CHIP CARRIER峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5 V最大电源电流（ICC）：53 mA
传播延迟（tpd）：14 ns认证状态：Not Qualified
座面最大高度：2.03 mm子类别：Counters
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：TTL温度等级：MILITARY
端子形式：NO LEAD端子节距：1.27 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
触发器类型：POSITIVE EDGE宽度：8.89 mm
最小 fmax：65 MHzBase Number Matches：1

SN54AS163FK 数据手册

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SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163  
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163  
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS  
SDAS276 – DECEMBER 1994  
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161,  
• Internal Look-Ahead Circuitry for Fast  
SN54AS163 . . . J PACKAGE  
SN74ALS161B, SN74ALS163B, SN74AS161,  
SN74AS163 . . . D OR N PACKAGE  
(TOP VIEW)  
Counting  
• Carry Output for n-Bit Cascading  
• Synchronous Counting  
• Synchronously Programmable  
• Package Options Include Plastic  
Small-Outline (D) Packages, Ceramic Chip  
Carriers (FK), and Standard Plastic (N) and  
Ceramic (J) 300-mil DIPs  
CLR  
CLK  
A
V
CC  
RCO  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
Q
A
B
C
D
Q
B
Q
C
Q
D
ENT  
description  
ENP  
GND  
LOAD  
These synchronous, presettable, 4-bit decade  
and binary counters feature an internal carry  
look-ahead circuitry for application in high-speed  
counting designs. The SN54ALS162B is a 4-bit  
decade counter. The ′ALS161B, ′ALS163B,  
′AS161, and ′AS163 are 4-bit binary counters.  
Synchronous operation is provided by having all  
flip-flops clocked simultaneously so that the  
outputs change coincidentally with each other  
when instructed by the count-enable (ENP, ENT)  
inputs and internal gating. This mode of operation  
eliminates the output counting spikes normally  
associated with asynchronous (ripple-clock)  
counters. A buffered clock (CLK) input triggers the  
four flip-flops on the rising (positive-going) edge of  
the clock input waveform.  
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161,  
SN54AS163 . . . FK PACKAGE  
(TOP VIEW)  
3
2
1
20 19  
18  
A
B
Q
Q
4
5
6
7
8
A
B
17  
16  
15  
14  
NC  
C
NC  
Q
C
D
Q
D
9 10 11 12 13  
These counters are fully programmable; they may  
be preset to any number between 0 and 9 or 15.  
Because presetting is synchronous, setting up a  
low level at the load (LOAD) input disables the  
counter and causes the outputs to agree with the  
setup data after the next clock pulse, regardless of  
the levels of the enable inputs.  
NC – No internal connection  
The clear function for the ′ALS161B and ′AS161 is asynchronous. A low level at the clear (CLR) input sets all  
four of the flip-flop outputs low, regardless of the levels of the CLK, LOAD, or enable inputs. The clear function  
for the SN54ALS162B, ′ALS163B, and ′AS163 is synchronous, and a low level at CLR sets all four of the flip-flop  
outputs low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear  
allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The  
active-low output of the gate used for decoding is connected to CLR to synchronously clear the counter to  
0000 (LLLL).  
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without  
additional gating. ENP and ENT inputs and a ripple-carry (RCO) output are instrumental in accomplishing this  
function. Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. RCO, thus enabled,  
produces a high-level pulse while the count is maximum (9 or 15 with Q high). The high-level overflow  
A
ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed,  
regardless of the level of CLK.  
Copyright 1994, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...14

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