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SN54AHCT125_10

更新时间： 2024-11-25 12:19:55
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QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS

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SN54AHCT125_10 数据手册

 浏览型号SN54AHCT125_10的Datasheet PDF文件第2页浏览型号SN54AHCT125_10的Datasheet PDF文件第3页浏览型号SN54AHCT125_10的Datasheet PDF文件第4页浏览型号SN54AHCT125_10的Datasheet PDF文件第5页浏览型号SN54AHCT125_10的Datasheet PDF文件第6页浏览型号SN54AHCT125_10的Datasheet PDF文件第7页 
SN54AHCT125, SN74AHCT125  
QUADRUPLE BUS BUFFER GATES  
WITH 3-STATE OUTPUTS  
SCLS264O − DECEMBER 1995 − REVISED JULY 2003  
D
D
Inputs Are TTL-Voltage Compatible  
D
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
− 1000-V Charged-Device Model (C101)  
SN54AHCT125 . . . FK PACKAGE  
(TOP VIEW)  
SN74AHCT125 . . . RGY PACKAGE  
(TOP VIEW)  
SN54AHCT125 . . . J OR W PACKAGE  
SN74AHCT125 . . . D, DB, DGV, N, NS,  
OR PW PACKAGE  
(TOP VIEW)  
1
14  
1OE  
1A  
1Y  
2OE  
2A  
2Y  
VCC  
13 4OE  
1
2
3
4
5
6
7
14  
3
2
1 20 19  
18  
4A  
NC  
4Y  
1Y  
NC  
2OE  
NC  
1A  
1Y  
2OE  
2A  
13 4OE  
12 4A  
2
3
4
5
6
4
5
6
7
8
17  
16  
12  
11  
10  
9
4A  
4Y  
3OE  
3A  
11  
10  
9
4Y  
3OE  
3A  
15 NC  
14  
9 10 11 12 13  
3OE  
2A  
2Y  
7
8
8
GND  
3Y  
NC − No internal connection  
description/ordering information  
The ’AHCT125 devices are quadruple bus buffer gates featuring independent line drivers with 3-state outputs.  
Each output is disabled when the associated output-enable (OE) input is high. When OE is low, the respective  
gate passes the data from the A input to its Y output.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
T
A
PACKAGE  
QFN − RGY  
PDIP − N  
Tape and reel  
Tube  
SN74AHCT125RGYR  
SN74AHCT125N  
HB125  
SN74AHCT125N  
Tube  
SN74AHCT125D  
SOIC − D  
AHCT125  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SN74AHCT125DR  
SN74AHCT125NSR  
SN74AHCT125DBR  
SN74AHCT125PW  
SN74AHCT125PWR  
SN74AHCT125DGVR  
SNJ54AHCT125J  
SNJ54AHCT125W  
SNJ54AHCT125FK  
−40°C to 85°C  
SOP − NS  
AHCT125  
HB125  
SSOP − DB  
TSSOP − PW  
HB125  
Tape and reel  
Tape and reel  
Tube  
TVSOP − DGV  
CDIP − J  
HB125  
SNJ54AHCT125J  
SNJ54AHCT125W  
SNJ54AHCT125FK  
CFP − W  
Tube  
−55°C to 125°C  
LCCC − FK  
Tube  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright © 2003, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...22

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