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SN54AHCT132WR PDF预览

SN54AHCT132WR

更新时间： 2024-11-06 13:00:23
品牌 Logo 应用领域
德州仪器 - TI 触发器输入元件
页数 文件大小 规格书
6页 97K
描述
AHCT/VHCT SERIES, QUAD 2-INPUT NAND GATE, CDFP14, CERAMIC, FP-14

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SN54AHCT132WR 技术参数

生命周期：Obsolete零件包装代码：DFP
包装说明：DFP,针数：14
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.84Is Samacsys：N
系列：AHCT/VHCTJESD-30 代码：R-GDFP-F14
长度：9.21 mm逻辑集成电路类型：NAND GATE
功能数量：4输入次数：2
端子数量：14最高工作温度：125 °C
最低工作温度：-55 °C封装主体材料：CERAMIC, GLASS-SEALED
封装代码：DFP封装形状：RECTANGULAR
封装形式：FLATPACK传播延迟（tpd）：8 ns
认证状态：Not Qualified座面最大高度：2.03 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子形式：FLAT端子节距：1.27 mm
端子位置：DUAL宽度：6.29 mm
Base Number Matches：1

SN54AHCT132WR 数据手册

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SN54AHCT132, SN74AHCT132  
QUADRUPLE POSITIVE-NAND GATES  
WITH SCHMITT-TRIGGER INPUTS  
SCLS366F – MAY 1997 – REVISED JANUARY 2000  
SN54AHCT132 . . . J OR W PACKAGE  
SN74AHCT132 . . . D, DB, DGV, N, OR PW PACKAGE  
(TOP VIEW)  
EPIC (Enhanced-Performance Implanted  
CMOS) Process  
Inputs Are TTL-Voltage Compatible  
1A  
1B  
V
CC  
Operation From Very Slow Input  
Transitions  
1
2
3
4
5
6
7
14  
13  
12  
11  
4B  
4A  
4Y  
1Y  
Temperature-Compensated Threshold  
Levels  
2A  
2B  
10 3B  
High Noise Immunity  
9
8
2Y  
3A  
3Y  
Same Pinouts as ’AHCT00  
GND  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
SN54AHCT132 . . . FK PACKAGE  
(TOP VIEW)  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
– 1000-V Charged-Device Model (C101)  
3
2
1 20 19  
18  
Package Options Include Plastic  
Small-Outline (D), Shrink Small-Outline  
(DB), Thin Very Small-Outline (DGV), Thin  
Shrink Small-Outline (PW), and Ceramic  
Flat (W) Packages, Ceramic Chip Carriers  
(FK), and Standard Plastic (N) and Ceramic  
(J) DIPs  
4A  
17 NC  
1Y  
NC  
2A  
4
5
6
7
8
16  
4Y  
NC  
3B  
15  
14  
NC  
2B  
9 10 11 12 13  
description  
NC – No internal connection  
The ’AHCT132 devices are quadruple  
positive-NAND gates.  
These devices perform the Boolean function Y = A • B or Y = A + B in positive logic.  
Each circuit functions as a NAND gate, but because of the Schmitt action, it has different input threshold levels  
for positive- and negative-going signals.  
These circuits are temperature compensated and can be triggered from the slowest of input ramps and still give  
clean jitter-free output signals.  
The SN54AHCT132 is characterized for operation over the full military temperature range of –55°C to 125°C.  
The SN74AHCT132 is characterized for operation from –40°C to 85°C.  
FUNCTION TABLE  
(each gate)  
INPUTS  
OUTPUT  
Y
A
B
H
X
L
H
L
L
H
H
X
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 2000, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
123456

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