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SN54AHC273W PDF预览

SN54AHC273W

更新时间: 2024-11-01 23:06:07
品牌 Logo 应用领域
德州仪器 - TI 触发器
页数 文件大小 规格书
7页 108K
描述
OCTAL D-TYPE FLIP-FLOPS WITH CLEAR

SN54AHC273W 技术参数

生命周期:Obsolete零件包装代码:DFP
包装说明:DFP,针数:20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.4系列:AHC
JESD-30 代码:R-GDFP-F20长度:13.09 mm
负载电容(CL):50 pF逻辑集成电路类型:D FLIP-FLOP
位数:8功能数量:1
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出极性:TRUE
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DFP
封装形状:RECTANGULAR封装形式:FLATPACK
传播延迟(tpd):19.5 ns认证状态:Not Qualified
座面最大高度:2.54 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子形式:FLAT
端子节距:1.27 mm端子位置:DUAL
触发器类型:POSITIVE EDGE宽度:6.92 mm
最小 fmax:100 MHzBase Number Matches:1

SN54AHC273W 数据手册

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SN54AHC273, SN74AHC273  
OCTAL D-TYPE FLIP-FLOPS  
WITH CLEAR  
SCLS376E – JUNE 1997 – REVISED JANUARY 2000  
SN54AHC273 . . . J OR W PACKAGE  
SN74AHC273 . . . DB, DGV, DW, N, OR PW PACKAGE  
(TOP VIEW)  
EPIC (Enhanced-Performance Implanted  
CMOS) Process  
Operating Range 2-V to 5.5-V V  
CC  
CLR  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
V
CC  
Contain Eight Flip-Flops With Single-Rail  
Outputs  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
8Q  
8D  
7D  
7Q  
6Q  
6D  
Direct Clear Input  
Individual Data Input to Each Flip-Flop  
Applications Include:  
– Buffer/Storage Registers  
– Shift Registers  
13 5D  
12 5Q  
– Pattern Generators  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
11  
GND  
CLK  
Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), Thin Very Small-Outline (DGV), Thin  
Shrink Small-Outline (PW), and Ceramic  
Flat (W) Packages, Ceramic Chip Carriers  
(FK), and Standard Plastic (N) and Ceramic  
(J) DIPs  
SN54AHC273 . . . FK PACKAGE  
(TOP VIEW)  
3
2
1
20 19  
18  
2D  
2Q  
3Q  
3D  
4D  
8D  
17 7D  
4
5
6
7
8
16  
15  
14  
7Q  
6Q  
6D  
description  
These circuits are positive-edge-triggered D-type  
flip-flops with a direct clear (CLR) input.  
9 10 11 12 13  
Information at the data (D) inputs meeting the  
setup time requirements is transferred to the  
Q outputs on the positive-going edge of the clock  
(CLK) pulse. Clock triggering occurs at a  
particular voltage level and is not directly related  
to the transition time of the positive-going pulse.  
When CLK is at either the high or low level, the  
D input has no effect at the output.  
The SN54AHC273 is characterized for operation over the full military temperature range of –55°C to 125°C.  
The SN74AHC273 is characterized for operation from –40°C to 85 °C.  
FUNCTION TABLE  
(each flip-flop)  
INPUTS  
OUTPUT  
Q
CLK  
D
X
H
L
CLR  
L
X
L
H
L
H
H
H
L
X
Q
0
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 2000, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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